Searched hist:f6bfe45a (Results 1 – 2 of 2) sorted by relevance
| /openbmc/qemu/include/hw/char/ |
| H A D | stm32f2xx_usart.h | f6bfe45a Thu Feb 22 09:12:51 CST 2018 Richard Braun <rbraun@sceen.net> hw/char/stm32f2xx_usart: fix TXE/TC bit handling
I/O currently being synchronous, there is no reason to ever clear the
SR_TXE bit. However the SR_TC bit may be cleared by software writing
to the SR register, so set it on each write.
In addition, fix the reset value of the USART status register.
Signed-off-by: Richard Braun <rbraun@sceen.net>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
[PMM: removed XXX tag from comment, since it isn't something
we need to come back and fix in QEMU]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|
| /openbmc/qemu/hw/char/ |
| H A D | stm32f2xx_usart.c | f6bfe45a Thu Feb 22 09:12:51 CST 2018 Richard Braun <rbraun@sceen.net> hw/char/stm32f2xx_usart: fix TXE/TC bit handling
I/O currently being synchronous, there is no reason to ever clear the
SR_TXE bit. However the SR_TC bit may be cleared by software writing
to the SR register, so set it on each write.
In addition, fix the reset value of the USART status register.
Signed-off-by: Richard Braun <rbraun@sceen.net>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
[PMM: removed XXX tag from comment, since it isn't something
we need to come back and fix in QEMU]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
|