Home
last modified time | relevance | path

Searched hist:e32d59a2fa6446b64167bba31c0dd40eb023e8bb (Results 1 – 4 of 4) sorted by relevance

/openbmc/u-boot/drivers/ddr/fsl/
H A Dutil.ce32d59a2fa6446b64167bba31c0dd40eb023e8bb Tue Jan 06 15:18:55 CST 2015 York Sun <yorksun@freescale.com> driver/ddr/fsl: Add sync of refresh

Add sync of refresh for multiple DDR controllers. DDRC initialization
needs to complete first. Code is re-ordered to keep refresh close.

Signed-off-by: York Sun <yorksun@freescale.com>
H A Dmain.ce32d59a2fa6446b64167bba31c0dd40eb023e8bb Tue Jan 06 15:18:55 CST 2015 York Sun <yorksun@freescale.com> driver/ddr/fsl: Add sync of refresh

Add sync of refresh for multiple DDR controllers. DDRC initialization
needs to complete first. Code is re-ordered to keep refresh close.

Signed-off-by: York Sun <yorksun@freescale.com>
/openbmc/u-boot/include/
H A Dfsl_ddr.he32d59a2fa6446b64167bba31c0dd40eb023e8bb Tue Jan 06 15:18:55 CST 2015 York Sun <yorksun@freescale.com> driver/ddr/fsl: Add sync of refresh

Add sync of refresh for multiple DDR controllers. DDRC initialization
needs to complete first. Code is re-ordered to keep refresh close.

Signed-off-by: York Sun <yorksun@freescale.com>
/openbmc/u-boot/
H A DREADMEe32d59a2fa6446b64167bba31c0dd40eb023e8bb Tue Jan 06 15:18:55 CST 2015 York Sun <yorksun@freescale.com> driver/ddr/fsl: Add sync of refresh

Add sync of refresh for multiple DDR controllers. DDRC initialization
needs to complete first. Code is re-ordered to keep refresh close.

Signed-off-by: York Sun <yorksun@freescale.com>