Searched hist:d5f0942b5066e28138476259d076e4d6c871da7d (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | intel,agilex5-clkmgr.yaml | d5f0942b5066e28138476259d076e4d6c871da7d Tue Aug 01 21:58:42 CDT 2023 Niravkumar L Rabara <niravkumar.l.rabara@intel.com> dt-bindings: clock: add Intel Agilex5 clock manager
Add clock ID definitions for Intel Agilex5 SoCFPGA.
The registers in Agilex5 handling the clock is named as clock manager.
Signed-off-by: Teh Wen Ping <wen.ping.teh@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | intel,agilex5-clkmgr.h | d5f0942b5066e28138476259d076e4d6c871da7d Tue Aug 01 21:58:42 CDT 2023 Niravkumar L Rabara <niravkumar.l.rabara@intel.com> dt-bindings: clock: add Intel Agilex5 clock manager
Add clock ID definitions for Intel Agilex5 SoCFPGA.
The registers in Agilex5 handling the clock is named as clock manager.
Signed-off-by: Teh Wen Ping <wen.ping.teh@intel.com>
Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
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