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/openbmc/qemu/hw/intc/
H A Darm_gicv3.cce187c3c Fri Jun 17 09:23:46 CDT 2016 Peter Maydell <peter.maydell@linaro.org> hw/intc/arm_gicv3: Implement functions to identify next pending irq

Implement the GICv3 logic to recalculate the highest priority pending
interrupt for each CPU after some part of the GIC state has changed.
We avoid unnecessary full recalculation where possible.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
Tested-by: Shannon Zhao <shannon.zhao@linaro.org>
Message-id: 1465915112-29272-11-git-send-email-peter.maydell@linaro.org
H A Dgicv3_internal.hce187c3c Fri Jun 17 09:23:46 CDT 2016 Peter Maydell <peter.maydell@linaro.org> hw/intc/arm_gicv3: Implement functions to identify next pending irq

Implement the GICv3 logic to recalculate the highest priority pending
interrupt for each CPU after some part of the GIC state has changed.
We avoid unnecessary full recalculation where possible.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
Tested-by: Shannon Zhao <shannon.zhao@linaro.org>
Message-id: 1465915112-29272-11-git-send-email-peter.maydell@linaro.org
H A Darm_gicv3_common.cce187c3c Fri Jun 17 09:23:46 CDT 2016 Peter Maydell <peter.maydell@linaro.org> hw/intc/arm_gicv3: Implement functions to identify next pending irq

Implement the GICv3 logic to recalculate the highest priority pending
interrupt for each CPU after some part of the GIC state has changed.
We avoid unnecessary full recalculation where possible.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
Tested-by: Shannon Zhao <shannon.zhao@linaro.org>
Message-id: 1465915112-29272-11-git-send-email-peter.maydell@linaro.org
/openbmc/qemu/include/hw/intc/
H A Darm_gicv3_common.hce187c3c Fri Jun 17 09:23:46 CDT 2016 Peter Maydell <peter.maydell@linaro.org> hw/intc/arm_gicv3: Implement functions to identify next pending irq

Implement the GICv3 logic to recalculate the highest priority pending
interrupt for each CPU after some part of the GIC state has changed.
We avoid unnecessary full recalculation where possible.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org>
Tested-by: Shannon Zhao <shannon.zhao@linaro.org>
Message-id: 1465915112-29272-11-git-send-email-peter.maydell@linaro.org