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H A Dmisc_helper.cc5d98a7b Thu Jun 22 04:33:52 CDT 2023 Nicholas Piggin <npiggin@gmail.com> target/ppc: Add support for SMT CTRL register

A relatively simple case to begin with, CTRL is a SMT shared register
where reads and writes need to synchronise against state changes by
other threads in the core.

Atomic serialisation operations are used to achieve this.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
H A Dhelper.hc5d98a7b Thu Jun 22 04:33:52 CDT 2023 Nicholas Piggin <npiggin@gmail.com> target/ppc: Add support for SMT CTRL register

A relatively simple case to begin with, CTRL is a SMT shared register
where reads and writes need to synchronise against state changes by
other threads in the core.

Atomic serialisation operations are used to achieve this.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
H A Dtranslate.cc5d98a7b Thu Jun 22 04:33:52 CDT 2023 Nicholas Piggin <npiggin@gmail.com> target/ppc: Add support for SMT CTRL register

A relatively simple case to begin with, CTRL is a SMT shared register
where reads and writes need to synchronise against state changes by
other threads in the core.

Atomic serialisation operations are used to achieve this.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>