Searched hist:bae120f8 (Results 1 – 3 of 3) sorted by relevance
| /openbmc/linux/arch/arm64/boot/dts/socionext/ |
| H A D | uniphier-pxs3.dtsi | bae120f8 Fri Jul 20 03:50:45 CDT 2018 Masahiro Yamada <yamada.masahiro@socionext.com> arm64: uniphier: dts: add more clocks to Denali NAND controller node
Catch up with the new binding of the Denali IP where three clocks,
"nand", "nand_x", "ecc" are required.
For UniPhier SoCs, the "nand_x" and "ecc" are tied up because they
are both 200MHz.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
bae120f8 Fri Jul 20 03:50:45 CDT 2018 Masahiro Yamada <yamada.masahiro@socionext.com> arm64: uniphier: dts: add more clocks to Denali NAND controller node
Catch up with the new binding of the Denali IP where three clocks,
"nand", "nand_x", "ecc" are required.
For UniPhier SoCs, the "nand_x" and "ecc" are tied up because they
are both 200MHz.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| H A D | uniphier-ld11.dtsi | bae120f8 Fri Jul 20 03:50:45 CDT 2018 Masahiro Yamada <yamada.masahiro@socionext.com> arm64: uniphier: dts: add more clocks to Denali NAND controller node
Catch up with the new binding of the Denali IP where three clocks,
"nand", "nand_x", "ecc" are required.
For UniPhier SoCs, the "nand_x" and "ecc" are tied up because they
are both 200MHz.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
bae120f8 Fri Jul 20 03:50:45 CDT 2018 Masahiro Yamada <yamada.masahiro@socionext.com> arm64: uniphier: dts: add more clocks to Denali NAND controller node
Catch up with the new binding of the Denali IP where three clocks,
"nand", "nand_x", "ecc" are required.
For UniPhier SoCs, the "nand_x" and "ecc" are tied up because they
are both 200MHz.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| H A D | uniphier-ld20.dtsi | bae120f8 Fri Jul 20 03:50:45 CDT 2018 Masahiro Yamada <yamada.masahiro@socionext.com> arm64: uniphier: dts: add more clocks to Denali NAND controller node
Catch up with the new binding of the Denali IP where three clocks,
"nand", "nand_x", "ecc" are required.
For UniPhier SoCs, the "nand_x" and "ecc" are tied up because they
are both 200MHz.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
bae120f8 Fri Jul 20 03:50:45 CDT 2018 Masahiro Yamada <yamada.masahiro@socionext.com> arm64: uniphier: dts: add more clocks to Denali NAND controller node
Catch up with the new binding of the Denali IP where three clocks,
"nand", "nand_x", "ecc" are required.
For UniPhier SoCs, the "nand_x" and "ecc" are tied up because they
are both 200MHz.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|