Searched hist:b9e0d40c (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | keystone-pll.txt | b9e0d40c Wed Sep 25 20:18:13 CDT 2013 Santosh Shilimkar <santosh.shilimkar@ti.com> clk: keystone: add Keystone PLL clock driver
Add the driver for the PLL IPs found on Keystone 2 devices. The PLL
IP typically has a multiplier, a divider and a post-divider. The PLL IPs like
ARMPLL, DDRPLL and PAPLL are controlled by the memory mapped register where
as the Main PLL is controlled by a PLL controller and memory map registers.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
b9e0d40c Wed Sep 25 20:18:13 CDT 2013 Santosh Shilimkar <santosh.shilimkar@ti.com> clk: keystone: add Keystone PLL clock driver
Add the driver for the PLL IPs found on Keystone 2 devices. The PLL
IP typically has a multiplier, a divider and a post-divider. The PLL IPs like
ARMPLL, DDRPLL and PAPLL are controlled by the memory mapped register where
as the Main PLL is controlled by a PLL controller and memory map registers.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
|
| /openbmc/linux/drivers/clk/keystone/ |
| H A D | pll.c | b9e0d40c Wed Sep 25 20:18:13 CDT 2013 Santosh Shilimkar <santosh.shilimkar@ti.com> clk: keystone: add Keystone PLL clock driver
Add the driver for the PLL IPs found on Keystone 2 devices. The PLL
IP typically has a multiplier, a divider and a post-divider. The PLL IPs like
ARMPLL, DDRPLL and PAPLL are controlled by the memory mapped register where
as the Main PLL is controlled by a PLL controller and memory map registers.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
b9e0d40c Wed Sep 25 20:18:13 CDT 2013 Santosh Shilimkar <santosh.shilimkar@ti.com> clk: keystone: add Keystone PLL clock driver
Add the driver for the PLL IPs found on Keystone 2 devices. The PLL
IP typically has a multiplier, a divider and a post-divider. The PLL IPs like
ARMPLL, DDRPLL and PAPLL are controlled by the memory mapped register where
as the Main PLL is controlled by a PLL controller and memory map registers.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
|