Searched hist:b71d0385 (Results 1 – 6 of 6) sorted by relevance
/openbmc/qemu/hw/misc/ |
H A D | allwinner-h3-dramc.c | b71d0385 Wed Mar 11 17:18:47 CDT 2020 Niek Linnenbank <nieklinnenbank@gmail.com> hw/arm/allwinner-h3: add SDRAM controller device In the Allwinner H3 SoC the SDRAM controller is responsible for interfacing with the external Synchronous Dynamic Random Access Memory (SDRAM). Types of memory that the SDRAM controller supports are DDR2/DDR3 and capacities of up to 2GiB. This commit adds emulation support of the Allwinner H3 SDRAM controller. Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200311221854.30370-12-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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H A D | trace-events | b71d0385 Wed Mar 11 17:18:47 CDT 2020 Niek Linnenbank <nieklinnenbank@gmail.com> hw/arm/allwinner-h3: add SDRAM controller device In the Allwinner H3 SoC the SDRAM controller is responsible for interfacing with the external Synchronous Dynamic Random Access Memory (SDRAM). Types of memory that the SDRAM controller supports are DDR2/DDR3 and capacities of up to 2GiB. This commit adds emulation support of the Allwinner H3 SDRAM controller. Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200311221854.30370-12-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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/openbmc/qemu/include/hw/misc/ |
H A D | allwinner-h3-dramc.h | b71d0385 Wed Mar 11 17:18:47 CDT 2020 Niek Linnenbank <nieklinnenbank@gmail.com> hw/arm/allwinner-h3: add SDRAM controller device In the Allwinner H3 SoC the SDRAM controller is responsible for interfacing with the external Synchronous Dynamic Random Access Memory (SDRAM). Types of memory that the SDRAM controller supports are DDR2/DDR3 and capacities of up to 2GiB. This commit adds emulation support of the Allwinner H3 SDRAM controller. Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200311221854.30370-12-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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/openbmc/qemu/include/hw/arm/ |
H A D | allwinner-h3.h | b71d0385 Wed Mar 11 17:18:47 CDT 2020 Niek Linnenbank <nieklinnenbank@gmail.com> hw/arm/allwinner-h3: add SDRAM controller device In the Allwinner H3 SoC the SDRAM controller is responsible for interfacing with the external Synchronous Dynamic Random Access Memory (SDRAM). Types of memory that the SDRAM controller supports are DDR2/DDR3 and capacities of up to 2GiB. This commit adds emulation support of the Allwinner H3 SDRAM controller. Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200311221854.30370-12-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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/openbmc/qemu/hw/arm/ |
H A D | allwinner-h3.c | b71d0385 Wed Mar 11 17:18:47 CDT 2020 Niek Linnenbank <nieklinnenbank@gmail.com> hw/arm/allwinner-h3: add SDRAM controller device In the Allwinner H3 SoC the SDRAM controller is responsible for interfacing with the external Synchronous Dynamic Random Access Memory (SDRAM). Types of memory that the SDRAM controller supports are DDR2/DDR3 and capacities of up to 2GiB. This commit adds emulation support of the Allwinner H3 SDRAM controller. Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200311221854.30370-12-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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H A D | orangepi.c | b71d0385 Wed Mar 11 17:18:47 CDT 2020 Niek Linnenbank <nieklinnenbank@gmail.com> hw/arm/allwinner-h3: add SDRAM controller device In the Allwinner H3 SoC the SDRAM controller is responsible for interfacing with the external Synchronous Dynamic Random Access Memory (SDRAM). Types of memory that the SDRAM controller supports are DDR2/DDR3 and capacities of up to 2GiB. This commit adds emulation support of the Allwinner H3 SDRAM controller. Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20200311221854.30370-12-nieklinnenbank@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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