Searched hist:a6922f4a (Results 1 – 5 of 5) sorted by relevance
/openbmc/linux/drivers/gpu/drm/i915/display/ |
H A D | intel_display_power.h | a6922f4a Tue May 11 23:21:40 CDT 2021 Matt Roper <matthew.d.roper@intel.com> drm/i915/xelpd: Add XE_LPD power wells
Aside from the hardware-managed PG0, XE_LPD has power wells 1-2 and A-D. These power wells should be enabled/disabled according to the following dependency tree (enable top to bottom, disable bottom to top):
PG0 | --PG1-- / \ PGA --PG2-- / | \ PGB PGC PGD
PWR_WELL_CTL follows the general ICL/TGL design and places PG A-D in the bits that would have been PG 6-9 under the old scheme.
PWR_WELL_CTL_{DDI,AUX}'s bit indexing for DDI's A-C and TC1 is the same as TGL, but DDI-D is placed at index 7 (bits 14 & 15).
v2: - Squash in LPSP status patch from Uma since it's also a powerwell-specific change.
Bspec: 49233 Bspec: 49503 Bspec: 49504 Bspec: 49505 Bspec: 49296 Bspec: 50090 Bspec: 53920 Cc: Anshuman Gupta <anshuman.gupta@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210512042144.2089071-4-matthew.d.roper@intel.com
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H A D | intel_vdsc.c | a6922f4a Tue May 11 23:21:40 CDT 2021 Matt Roper <matthew.d.roper@intel.com> drm/i915/xelpd: Add XE_LPD power wells
Aside from the hardware-managed PG0, XE_LPD has power wells 1-2 and A-D. These power wells should be enabled/disabled according to the following dependency tree (enable top to bottom, disable bottom to top):
PG0 | --PG1-- / \ PGA --PG2-- / | \ PGB PGC PGD
PWR_WELL_CTL follows the general ICL/TGL design and places PG A-D in the bits that would have been PG 6-9 under the old scheme.
PWR_WELL_CTL_{DDI,AUX}'s bit indexing for DDI's A-C and TC1 is the same as TGL, but DDI-D is placed at index 7 (bits 14 & 15).
v2: - Squash in LPSP status patch from Uma since it's also a powerwell-specific change.
Bspec: 49233 Bspec: 49503 Bspec: 49504 Bspec: 49505 Bspec: 49296 Bspec: 50090 Bspec: 53920 Cc: Anshuman Gupta <anshuman.gupta@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210512042144.2089071-4-matthew.d.roper@intel.com
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H A D | intel_display_debugfs.c | a6922f4a Tue May 11 23:21:40 CDT 2021 Matt Roper <matthew.d.roper@intel.com> drm/i915/xelpd: Add XE_LPD power wells
Aside from the hardware-managed PG0, XE_LPD has power wells 1-2 and A-D. These power wells should be enabled/disabled according to the following dependency tree (enable top to bottom, disable bottom to top):
PG0 | --PG1-- / \ PGA --PG2-- / | \ PGB PGC PGD
PWR_WELL_CTL follows the general ICL/TGL design and places PG A-D in the bits that would have been PG 6-9 under the old scheme.
PWR_WELL_CTL_{DDI,AUX}'s bit indexing for DDI's A-C and TC1 is the same as TGL, but DDI-D is placed at index 7 (bits 14 & 15).
v2: - Squash in LPSP status patch from Uma since it's also a powerwell-specific change.
Bspec: 49233 Bspec: 49503 Bspec: 49504 Bspec: 49505 Bspec: 49296 Bspec: 50090 Bspec: 53920 Cc: Anshuman Gupta <anshuman.gupta@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210512042144.2089071-4-matthew.d.roper@intel.com
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H A D | intel_display_power.c | a6922f4a Tue May 11 23:21:40 CDT 2021 Matt Roper <matthew.d.roper@intel.com> drm/i915/xelpd: Add XE_LPD power wells
Aside from the hardware-managed PG0, XE_LPD has power wells 1-2 and A-D. These power wells should be enabled/disabled according to the following dependency tree (enable top to bottom, disable bottom to top):
PG0 | --PG1-- / \ PGA --PG2-- / | \ PGB PGC PGD
PWR_WELL_CTL follows the general ICL/TGL design and places PG A-D in the bits that would have been PG 6-9 under the old scheme.
PWR_WELL_CTL_{DDI,AUX}'s bit indexing for DDI's A-C and TC1 is the same as TGL, but DDI-D is placed at index 7 (bits 14 & 15).
v2: - Squash in LPSP status patch from Uma since it's also a powerwell-specific change.
Bspec: 49233 Bspec: 49503 Bspec: 49504 Bspec: 49505 Bspec: 49296 Bspec: 50090 Bspec: 53920 Cc: Anshuman Gupta <anshuman.gupta@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210512042144.2089071-4-matthew.d.roper@intel.com
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/openbmc/linux/drivers/gpu/drm/i915/ |
H A D | i915_reg.h | a6922f4a Tue May 11 23:21:40 CDT 2021 Matt Roper <matthew.d.roper@intel.com> drm/i915/xelpd: Add XE_LPD power wells
Aside from the hardware-managed PG0, XE_LPD has power wells 1-2 and A-D. These power wells should be enabled/disabled according to the following dependency tree (enable top to bottom, disable bottom to top):
PG0 | --PG1-- / \ PGA --PG2-- / | \ PGB PGC PGD
PWR_WELL_CTL follows the general ICL/TGL design and places PG A-D in the bits that would have been PG 6-9 under the old scheme.
PWR_WELL_CTL_{DDI,AUX}'s bit indexing for DDI's A-C and TC1 is the same as TGL, but DDI-D is placed at index 7 (bits 14 & 15).
v2: - Squash in LPSP status patch from Uma since it's also a powerwell-specific change.
Bspec: 49233 Bspec: 49503 Bspec: 49504 Bspec: 49505 Bspec: 49296 Bspec: 50090 Bspec: 53920 Cc: Anshuman Gupta <anshuman.gupta@intel.com> Cc: Imre Deak <imre.deak@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Uma Shankar <uma.shankar@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210512042144.2089071-4-matthew.d.roper@intel.com
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