1df0566a6SJani Nikula /* SPDX-License-Identifier: MIT */
2df0566a6SJani Nikula /*
3df0566a6SJani Nikula * Copyright © 2019 Intel Corporation
4df0566a6SJani Nikula */
5df0566a6SJani Nikula
6df0566a6SJani Nikula #ifndef __INTEL_DISPLAY_POWER_H__
7df0566a6SJani Nikula #define __INTEL_DISPLAY_POWER_H__
8df0566a6SJani Nikula
9*5b782635SImre Deak #include <linux/mutex.h>
10*5b782635SImre Deak #include <linux/workqueue.h>
11*5b782635SImre Deak
1250ae1a1cSJani Nikula #include "intel_wakeref.h"
13df0566a6SJani Nikula
14979e1b32SImre Deak enum aux_ch;
155ed597daSJani Nikula enum port;
165ed597daSJani Nikula struct drm_i915_private;
1750ae1a1cSJani Nikula struct i915_power_well;
18979e1b32SImre Deak struct intel_encoder;
19df0566a6SJani Nikula struct seq_file;
20de511df7SJani Nikula
21df0566a6SJani Nikula /*
22*5b782635SImre Deak * Keep the pipe, transcoder, port (DDI_LANES,DDI_IO,AUX) domain instances
23df0566a6SJani Nikula * consecutive, so that the pipe,transcoder,port -> power domain macros
24492c1ae2SImre Deak * work correctly.
25492c1ae2SImre Deak */
26492c1ae2SImre Deak enum intel_display_power_domain {
27492c1ae2SImre Deak POWER_DOMAIN_DISPLAY_CORE,
28492c1ae2SImre Deak POWER_DOMAIN_PIPE_A,
29df0566a6SJani Nikula POWER_DOMAIN_PIPE_B,
30df0566a6SJani Nikula POWER_DOMAIN_PIPE_C,
31df0566a6SJani Nikula POWER_DOMAIN_PIPE_D,
32df0566a6SJani Nikula POWER_DOMAIN_PIPE_PANEL_FITTER_A,
33df0566a6SJani Nikula POWER_DOMAIN_PIPE_PANEL_FITTER_B,
341db27a72SMika Kahola POWER_DOMAIN_PIPE_PANEL_FITTER_C,
350ba2661dSImre Deak POWER_DOMAIN_PIPE_PANEL_FITTER_D,
360ba2661dSImre Deak POWER_DOMAIN_TRANSCODER_A,
370ba2661dSImre Deak POWER_DOMAIN_TRANSCODER_B,
380ba2661dSImre Deak POWER_DOMAIN_TRANSCODER_C,
39df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_D,
40df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_EDP,
41df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_DSI_A,
421db27a72SMika Kahola POWER_DOMAIN_TRANSCODER_DSI_C,
43df0566a6SJani Nikula
44df0566a6SJani Nikula /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */
45df0566a6SJani Nikula POWER_DOMAIN_TRANSCODER_VDSC_PW2,
46492c1ae2SImre Deak
47492c1ae2SImre Deak POWER_DOMAIN_PORT_DDI_LANES_A,
48492c1ae2SImre Deak POWER_DOMAIN_PORT_DDI_LANES_B,
49492c1ae2SImre Deak POWER_DOMAIN_PORT_DDI_LANES_C,
500ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_LANES_D,
510ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_LANES_E,
520ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_LANES_F,
530ba2661dSImre Deak
540ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC1,
550ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC2,
56c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC3,
57c97bbab0SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC4,
58c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC5,
59c7392718SImre Deak POWER_DOMAIN_PORT_DDI_LANES_TC6,
60c7392718SImre Deak
61c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_A,
62c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_B,
63c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_C,
640ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_IO_D,
650ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_IO_E,
660ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_IO_F,
670ba2661dSImre Deak
680ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_IO_TC1,
690ba2661dSImre Deak POWER_DOMAIN_PORT_DDI_IO_TC2,
70c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC3,
71c97bbab0SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC4,
72c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC5,
73c7392718SImre Deak POWER_DOMAIN_PORT_DDI_IO_TC6,
74c7392718SImre Deak
75c7392718SImre Deak POWER_DOMAIN_PORT_DSI,
76c7392718SImre Deak POWER_DOMAIN_PORT_CRT,
77c7392718SImre Deak POWER_DOMAIN_PORT_OTHER,
78df0566a6SJani Nikula POWER_DOMAIN_VGA,
79df0566a6SJani Nikula POWER_DOMAIN_AUDIO_MMIO,
80df0566a6SJani Nikula POWER_DOMAIN_AUDIO_PLAYBACK,
81df0566a6SJani Nikula
82615a7724SAnshuman Gupta POWER_DOMAIN_AUX_IO_A,
83615a7724SAnshuman Gupta POWER_DOMAIN_AUX_IO_B,
845c30cfcdSImre Deak POWER_DOMAIN_AUX_IO_C,
855c30cfcdSImre Deak POWER_DOMAIN_AUX_IO_D,
86f645cbdaSImre Deak POWER_DOMAIN_AUX_IO_E,
87f645cbdaSImre Deak POWER_DOMAIN_AUX_IO_F,
88f645cbdaSImre Deak
89f645cbdaSImre Deak POWER_DOMAIN_AUX_A,
90f645cbdaSImre Deak POWER_DOMAIN_AUX_B,
915c30cfcdSImre Deak POWER_DOMAIN_AUX_C,
92df0566a6SJani Nikula POWER_DOMAIN_AUX_D,
93df0566a6SJani Nikula POWER_DOMAIN_AUX_E,
94df0566a6SJani Nikula POWER_DOMAIN_AUX_F,
95df0566a6SJani Nikula
96df0566a6SJani Nikula POWER_DOMAIN_AUX_USBC1,
97df0566a6SJani Nikula POWER_DOMAIN_AUX_USBC2,
98c7392718SImre Deak POWER_DOMAIN_AUX_USBC3,
99c97bbab0SImre Deak POWER_DOMAIN_AUX_USBC4,
100c7392718SImre Deak POWER_DOMAIN_AUX_USBC5,
101c7392718SImre Deak POWER_DOMAIN_AUX_USBC6,
102c7392718SImre Deak
103c7392718SImre Deak POWER_DOMAIN_AUX_TBT1,
104c7392718SImre Deak POWER_DOMAIN_AUX_TBT2,
105c7392718SImre Deak POWER_DOMAIN_AUX_TBT3,
106c97bbab0SImre Deak POWER_DOMAIN_AUX_TBT4,
107c7392718SImre Deak POWER_DOMAIN_AUX_TBT5,
108c7392718SImre Deak POWER_DOMAIN_AUX_TBT6,
109c7392718SImre Deak
110c7392718SImre Deak POWER_DOMAIN_GMBUS,
111c7392718SImre Deak POWER_DOMAIN_MODESET,
112c7392718SImre Deak POWER_DOMAIN_GT_IRQ,
113df0566a6SJani Nikula POWER_DOMAIN_DC_OFF,
114df0566a6SJani Nikula POWER_DOMAIN_TC_COLD_OFF,
115df0566a6SJani Nikula POWER_DOMAIN_INIT,
116808b79ebSJosé Roberto de Souza
1173c02934bSJosé Roberto de Souza POWER_DOMAIN_NUM,
118df0566a6SJani Nikula POWER_DOMAIN_INVALID = POWER_DOMAIN_NUM,
119df0566a6SJani Nikula };
120df0566a6SJani Nikula
121979e1b32SImre Deak #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
122df0566a6SJani Nikula #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
123df0566a6SJani Nikula ((pipe) + POWER_DOMAIN_PIPE_PANEL_FITTER_A)
124df0566a6SJani Nikula #define POWER_DOMAIN_TRANSCODER(tran) \
125df0566a6SJani Nikula ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
1260ba2661dSImre Deak (tran) + POWER_DOMAIN_TRANSCODER_A)
127df0566a6SJani Nikula
128df0566a6SJani Nikula struct intel_power_domain_mask {
129df0566a6SJani Nikula DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);
130df0566a6SJani Nikula };
131888a2a63SImre Deak
132888a2a63SImre Deak struct i915_power_domains {
133888a2a63SImre Deak /*
134888a2a63SImre Deak * Power wells needed for initialization at driver init and suspend
135df0566a6SJani Nikula * time are on. They are kept on until after the first modeset.
136df0566a6SJani Nikula */
137df0566a6SJani Nikula bool initializing;
138df0566a6SJani Nikula bool display_core_suspended;
139df0566a6SJani Nikula int power_well_count;
140df0566a6SJani Nikula
141df0566a6SJani Nikula u32 dc_state;
142df0566a6SJani Nikula u32 target_dc_state;
143df0566a6SJani Nikula u32 allowed_dc_mask;
144825f0de2SJani Nikula
145825f0de2SJani Nikula intel_wakeref_t init_wakeref;
146825f0de2SJani Nikula intel_wakeref_t disable_wakeref;
147825f0de2SJani Nikula
148a0b024edSImre Deak struct mutex lock;
14993b916fdSImre Deak int domain_use_count[POWER_DOMAIN_NUM];
150df0566a6SJani Nikula
151df0566a6SJani Nikula struct delayed_work async_put_work;
152df0566a6SJani Nikula intel_wakeref_t async_put_wakeref;
153df0566a6SJani Nikula struct intel_power_domain_mask async_put_domains[2];
154df0566a6SJani Nikula int async_put_next_delay;
155df0566a6SJani Nikula
156888a2a63SImre Deak struct i915_power_well *power_wells;
157df0566a6SJani Nikula };
158df0566a6SJani Nikula
159df0566a6SJani Nikula struct intel_display_power_domain_set {
160df0566a6SJani Nikula struct intel_power_domain_mask mask;
1616979cb9aSImre Deak #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM
162888a2a63SImre Deak intel_wakeref_t wakerefs[POWER_DOMAIN_NUM];
1636979cb9aSImre Deak #endif
1646979cb9aSImre Deak };
1656979cb9aSImre Deak
1666979cb9aSImre Deak #define for_each_power_domain(__domain, __mask) \
1676979cb9aSImre Deak for ((__domain) = 0; (__domain) < POWER_DOMAIN_NUM; (__domain)++) \
168888a2a63SImre Deak for_each_if(test_bit((__domain), (__mask)->bits))
169888a2a63SImre Deak
170888a2a63SImre Deak int intel_power_domains_init(struct drm_i915_private *dev_priv);
171df0566a6SJani Nikula void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
172df0566a6SJani Nikula void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
173df0566a6SJani Nikula void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv);
174df0566a6SJani Nikula void intel_power_domains_enable(struct drm_i915_private *dev_priv);
17578dae1acSJanusz Krzysztofik void intel_power_domains_disable(struct drm_i915_private *dev_priv);
176df0566a6SJani Nikula void intel_power_domains_suspend(struct drm_i915_private *dev_priv, bool s2idle);
177df0566a6SJani Nikula void intel_power_domains_resume(struct drm_i915_private *dev_priv);
178c7b5abd3SMaarten Lankhorst void intel_power_domains_sanitize_state(struct drm_i915_private *dev_priv);
179df0566a6SJani Nikula
180d946bc44SImre Deak void intel_display_power_suspend_late(struct drm_i915_private *i915);
181071b68ccSRodrigo Vivi void intel_display_power_resume_early(struct drm_i915_private *i915);
182071b68ccSRodrigo Vivi void intel_display_power_suspend(struct drm_i915_private *i915);
183071b68ccSRodrigo Vivi void intel_display_power_resume(struct drm_i915_private *i915);
184071b68ccSRodrigo Vivi void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
185071b68ccSRodrigo Vivi u32 state);
1861c4d821dSAnshuman Gupta
1871c4d821dSAnshuman Gupta const char *
188df0566a6SJani Nikula intel_display_power_domain_str(enum intel_display_power_domain domain);
189df0566a6SJani Nikula
1908a84bacbSImre Deak bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
191df0566a6SJani Nikula enum intel_display_power_domain domain);
192df0566a6SJani Nikula bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
193df0566a6SJani Nikula enum intel_display_power_domain domain);
194df0566a6SJani Nikula intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
195df0566a6SJani Nikula enum intel_display_power_domain domain);
196df0566a6SJani Nikula intel_wakeref_t
197df0566a6SJani Nikula intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
198df0566a6SJani Nikula enum intel_display_power_domain domain);
199df0566a6SJani Nikula void __intel_display_power_put_async(struct drm_i915_private *i915,
200df0566a6SJani Nikula enum intel_display_power_domain domain,
201df0566a6SJani Nikula intel_wakeref_t wakeref,
202df0566a6SJani Nikula int delay_ms);
203df0566a6SJani Nikula void intel_display_power_flush_work(struct drm_i915_private *i915);
204df0566a6SJani Nikula #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
205df0566a6SJani Nikula void intel_display_power_put(struct drm_i915_private *dev_priv,
206df0566a6SJani Nikula enum intel_display_power_domain domain,
207df0566a6SJani Nikula intel_wakeref_t wakeref);
208df0566a6SJani Nikula static inline void
intel_display_power_put_async(struct drm_i915_private * i915,enum intel_display_power_domain domain,intel_wakeref_t wakeref)209df0566a6SJani Nikula intel_display_power_put_async(struct drm_i915_private *i915,
210df0566a6SJani Nikula enum intel_display_power_domain domain,
211df0566a6SJani Nikula intel_wakeref_t wakeref)
212df0566a6SJani Nikula {
213df0566a6SJani Nikula __intel_display_power_put_async(i915, domain, wakeref, -1);
214df0566a6SJani Nikula }
215df0566a6SJani Nikula
216df0566a6SJani Nikula static inline void
intel_display_power_put_async_delay(struct drm_i915_private * i915,enum intel_display_power_domain domain,intel_wakeref_t wakeref,int delay_ms)217e3529346SImre Deak intel_display_power_put_async_delay(struct drm_i915_private *i915,
218e3529346SImre Deak enum intel_display_power_domain domain,
219e3529346SImre Deak intel_wakeref_t wakeref,
220df0566a6SJani Nikula int delay_ms)
221df0566a6SJani Nikula {
222df0566a6SJani Nikula __intel_display_power_put_async(i915, domain, wakeref, delay_ms);
223df0566a6SJani Nikula }
224df0566a6SJani Nikula #else
225df0566a6SJani Nikula void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
226df0566a6SJani Nikula enum intel_display_power_domain domain);
227df0566a6SJani Nikula
228df0566a6SJani Nikula static inline void
intel_display_power_put(struct drm_i915_private * i915,enum intel_display_power_domain domain,intel_wakeref_t wakeref)229df0566a6SJani Nikula intel_display_power_put(struct drm_i915_private *i915,
230df0566a6SJani Nikula enum intel_display_power_domain domain,
231df0566a6SJani Nikula intel_wakeref_t wakeref)
232df0566a6SJani Nikula {
233df0566a6SJani Nikula intel_display_power_put_unchecked(i915, domain);
234df0566a6SJani Nikula }
235df0566a6SJani Nikula
236df0566a6SJani Nikula static inline void
intel_display_power_put_async(struct drm_i915_private * i915,enum intel_display_power_domain domain,intel_wakeref_t wakeref)2376979cb9aSImre Deak intel_display_power_put_async(struct drm_i915_private *i915,
2386979cb9aSImre Deak enum intel_display_power_domain domain,
2396979cb9aSImre Deak intel_wakeref_t wakeref)
2406979cb9aSImre Deak {
2416979cb9aSImre Deak __intel_display_power_put_async(i915, domain, -1, -1);
2426979cb9aSImre Deak }
2436979cb9aSImre Deak
2446979cb9aSImre Deak static inline void
intel_display_power_put_async_delay(struct drm_i915_private * i915,enum intel_display_power_domain domain,intel_wakeref_t wakeref,int delay_ms)2456979cb9aSImre Deak intel_display_power_put_async_delay(struct drm_i915_private *i915,
2466979cb9aSImre Deak enum intel_display_power_domain domain,
2476979cb9aSImre Deak intel_wakeref_t wakeref,
2486979cb9aSImre Deak int delay_ms)
2496979cb9aSImre Deak {
250888a2a63SImre Deak __intel_display_power_put_async(i915, domain, -1, delay_ms);
2516979cb9aSImre Deak }
2526979cb9aSImre Deak #endif
2536979cb9aSImre Deak
2546979cb9aSImre Deak void
2556979cb9aSImre Deak intel_display_power_get_in_set(struct drm_i915_private *i915,
256888a2a63SImre Deak struct intel_display_power_domain_set *power_domain_set,
2576979cb9aSImre Deak enum intel_display_power_domain domain);
2586979cb9aSImre Deak
2596abf2fc0SJani Nikula bool
2606abf2fc0SJani Nikula intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
261979e1b32SImre Deak struct intel_display_power_domain_set *power_domain_set,
262979e1b32SImre Deak enum intel_display_power_domain domain);
263979e1b32SImre Deak
264979e1b32SImre Deak void
265979e1b32SImre Deak intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
266f645cbdaSImre Deak struct intel_display_power_domain_set *power_domain_set,
267f645cbdaSImre Deak struct intel_power_domain_mask *mask);
268979e1b32SImre Deak
269979e1b32SImre Deak static inline void
intel_display_power_put_all_in_set(struct drm_i915_private * i915,struct intel_display_power_domain_set * power_domain_set)270979e1b32SImre Deak intel_display_power_put_all_in_set(struct drm_i915_private *i915,
271979e1b32SImre Deak struct intel_display_power_domain_set *power_domain_set)
27249f75634SMatt Roper {
27349f75634SMatt Roper intel_display_power_put_mask_in_set(i915, power_domain_set, &power_domain_set->mask);
27449f75634SMatt Roper }
27549f75634SMatt Roper
2762570b7e3SStanislav Lisovskiy void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m);
2772570b7e3SStanislav Lisovskiy
2782570b7e3SStanislav Lisovskiy enum intel_display_power_domain
2798398024bSMatt Roper intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port);
2808398024bSMatt Roper enum intel_display_power_domain
2818435576bSStanislav Lisovskiy intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port);
2822570b7e3SStanislav Lisovskiy enum intel_display_power_domain
2832570b7e3SStanislav Lisovskiy intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
28456f48c1dSVille Syrjälä enum intel_display_power_domain
28556f48c1dSVille Syrjälä intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
28656f48c1dSVille Syrjälä enum intel_display_power_domain
287df0566a6SJani Nikula intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
288df0566a6SJani Nikula
289df0566a6SJani Nikula /*
290df0566a6SJani Nikula * FIXME: We should probably switch this to a 0-based scheme to be consistent
291c98e3d15SVille Syrjälä * with how we now name/number DBUF_CTL instances.
292c98e3d15SVille Syrjälä */
293c98e3d15SVille Syrjälä enum dbuf_slice {
294c98e3d15SVille Syrjälä DBUF_S1,
295df0566a6SJani Nikula DBUF_S2,
296 DBUF_S3,
297 DBUF_S4,
298 I915_MAX_DBUF_SLICES
299 };
300
301 void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
302 u8 req_slices);
303
304 #define with_intel_display_power(i915, domain, wf) \
305 for ((wf) = intel_display_power_get((i915), (domain)); (wf); \
306 intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
307
308 #define with_intel_display_power_if_enabled(i915, domain, wf) \
309 for ((wf) = intel_display_power_get_if_enabled((i915), (domain)); (wf); \
310 intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
311
312 #endif /* __INTEL_DISPLAY_POWER_H__ */
313