Searched hist:a0f6d926 (Results 1 – 4 of 4) sorted by relevance
| /openbmc/linux/drivers/gpu/drm/amd/include/ |
| H A D | navi14_ip_offset.h | a0f6d926 Mon Dec 17 04:24:03 CST 2018 Xiaojie Yuan <xiaojie.yuan@amd.com> drm/amdgpu/soc15: initialize reg base for navi14 (v2)
Initialize the IP register base offsets for navi14.
v2: squash in MP, CLK, THM updates
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
a0f6d926 Mon Dec 17 04:24:03 CST 2018 Xiaojie Yuan <xiaojie.yuan@amd.com> drm/amdgpu/soc15: initialize reg base for navi14 (v2)
Initialize the IP register base offsets for navi14.
v2: squash in MP, CLK, THM updates
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | nv.h | a0f6d926 Mon Dec 17 04:24:03 CST 2018 Xiaojie Yuan <xiaojie.yuan@amd.com> drm/amdgpu/soc15: initialize reg base for navi14 (v2)
Initialize the IP register base offsets for navi14.
v2: squash in MP, CLK, THM updates
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
a0f6d926 Mon Dec 17 04:24:03 CST 2018 Xiaojie Yuan <xiaojie.yuan@amd.com> drm/amdgpu/soc15: initialize reg base for navi14 (v2)
Initialize the IP register base offsets for navi14.
v2: squash in MP, CLK, THM updates
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| H A D | nv.c | a0f6d926 Mon Dec 17 04:24:03 CST 2018 Xiaojie Yuan <xiaojie.yuan@amd.com> drm/amdgpu/soc15: initialize reg base for navi14 (v2)
Initialize the IP register base offsets for navi14.
v2: squash in MP, CLK, THM updates
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
a0f6d926 Mon Dec 17 04:24:03 CST 2018 Xiaojie Yuan <xiaojie.yuan@amd.com> drm/amdgpu/soc15: initialize reg base for navi14 (v2)
Initialize the IP register base offsets for navi14.
v2: squash in MP, CLK, THM updates
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| H A D | Makefile | a0f6d926 Mon Dec 17 04:24:03 CST 2018 Xiaojie Yuan <xiaojie.yuan@amd.com> drm/amdgpu/soc15: initialize reg base for navi14 (v2)
Initialize the IP register base offsets for navi14.
v2: squash in MP, CLK, THM updates
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
a0f6d926 Mon Dec 17 04:24:03 CST 2018 Xiaojie Yuan <xiaojie.yuan@amd.com> drm/amdgpu/soc15: initialize reg base for navi14 (v2)
Initialize the IP register base offsets for navi14.
v2: squash in MP, CLK, THM updates
Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Jack Xiao <Jack.Xiao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|