Searched hist:"9691 c5b9" (Results 1 – 3 of 3) sorted by relevance
/openbmc/u-boot/board/freescale/mx53ard/ |
H A D | imximage_dd3.cfg | 9691c5b9 Thu Aug 18 22:28:10 CDT 2011 Fabio Estevam <festevam@gmail.com> mx53: ddr3: Update DD3 initialization Updated mx53 ddr3 script in order to align with the latest Freescale version from July 8, 2011: -change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz) -change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from "0x092080b0". This changes write recovery from 8 clocks to 6 clocks (in line with ESDCFG1[tWR]) Signed-off-by: Lily Zhang <r58066@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
|
/openbmc/u-boot/board/freescale/mx53smd/ |
H A D | imximage.cfg | 9691c5b9 Thu Aug 18 22:28:10 CDT 2011 Fabio Estevam <festevam@gmail.com> mx53: ddr3: Update DD3 initialization Updated mx53 ddr3 script in order to align with the latest Freescale version from July 8, 2011: -change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz) -change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from "0x092080b0". This changes write recovery from 8 clocks to 6 clocks (in line with ESDCFG1[tWR]) Signed-off-by: Lily Zhang <r58066@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
|
/openbmc/u-boot/board/freescale/mx53loco/ |
H A D | imximage.cfg | 9691c5b9 Thu Aug 18 22:28:10 CDT 2011 Fabio Estevam <festevam@gmail.com> mx53: ddr3: Update DD3 initialization Updated mx53 ddr3 script in order to align with the latest Freescale version from July 8, 2011: -change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz) -change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from "0x092080b0". This changes write recovery from 8 clocks to 6 clocks (in line with ESDCFG1[tWR]) Signed-off-by: Lily Zhang <r58066@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
|