Searched hist:"96765 cc4" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/include/soc/tegra/ |
| H A D | fuse.h | 96765cc4 Wed May 11 15:16:43 CDT 2022 Sumit Gupta <sumitg@nvidia.com> soc/tegra: Set ERD bit to mask inband errors
Add a function to set the ERD (Error Response Disable) bit in the
MISCREG_CCROC_ERR_CONFIG register from the Control Backbone (CBB) error
handler driver.
ERD bit allows masking of SError due to inband errors which are caused
by illegal register accesses through CBB. When the bit is set, interrupt
is used for reporting errors and magic code '0xdead2003' is returned.
This change is only required for Tegra194 SoC as the config is moved to
CBB register space for future SoC's. Also, remove unmapping the
apbmisc_base as it's required to get the base address for accessing the
misc register.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|
| /openbmc/linux/drivers/soc/tegra/fuse/ |
| H A D | tegra-apbmisc.c | 96765cc4 Wed May 11 15:16:43 CDT 2022 Sumit Gupta <sumitg@nvidia.com> soc/tegra: Set ERD bit to mask inband errors
Add a function to set the ERD (Error Response Disable) bit in the
MISCREG_CCROC_ERR_CONFIG register from the Control Backbone (CBB) error
handler driver.
ERD bit allows masking of SError due to inband errors which are caused
by illegal register accesses through CBB. When the bit is set, interrupt
is used for reporting errors and magic code '0xdead2003' is returned.
This change is only required for Tegra194 SoC as the config is moved to
CBB register space for future SoC's. Also, remove unmapping the
apbmisc_base as it's required to get the base address for accessing the
misc register.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
|