19952f691SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */
2306a7f91SThierry Reding /*
3*d9443646SStefan Kristiansson * Copyright (c) 2012-2023, NVIDIA CORPORATION. All rights reserved.
4306a7f91SThierry Reding */
5306a7f91SThierry Reding
6306a7f91SThierry Reding #ifndef __SOC_TEGRA_FUSE_H__
7306a7f91SThierry Reding #define __SOC_TEGRA_FUSE_H__
8306a7f91SThierry Reding
945e93440SDmitry Osipenko #include <linux/types.h>
1045e93440SDmitry Osipenko
11304664eaSThierry Reding #define TEGRA20 0x20
12304664eaSThierry Reding #define TEGRA30 0x30
13304664eaSThierry Reding #define TEGRA114 0x35
14304664eaSThierry Reding #define TEGRA124 0x40
1524ef5745SThierry Reding #define TEGRA132 0x13
160dc5a0d8SThierry Reding #define TEGRA210 0x21
1746011d43SSandipan Patra #define TEGRA186 0x18
1846011d43SSandipan Patra #define TEGRA194 0x19
191f44febfSThierry Reding #define TEGRA234 0x23
20*d9443646SStefan Kristiansson #define TEGRA264 0x26
21304664eaSThierry Reding
22783c8f4cSPeter De Schrijver #define TEGRA_FUSE_SKU_CALIB_0 0xf0
23783c8f4cSPeter De Schrijver #define TEGRA30_FUSE_SATA_CALIB 0x124
2487d66f28SThierry Reding #define TEGRA_FUSE_USB_CALIB_EXT_0 0x250
25783c8f4cSPeter De Schrijver
26304664eaSThierry Reding #ifndef __ASSEMBLY__
27304664eaSThierry Reding
2835874f36SPeter De Schrijver enum tegra_revision {
2935874f36SPeter De Schrijver TEGRA_REVISION_UNKNOWN = 0,
3035874f36SPeter De Schrijver TEGRA_REVISION_A01,
3135874f36SPeter De Schrijver TEGRA_REVISION_A02,
3235874f36SPeter De Schrijver TEGRA_REVISION_A03,
3335874f36SPeter De Schrijver TEGRA_REVISION_A03p,
3435874f36SPeter De Schrijver TEGRA_REVISION_A04,
3535874f36SPeter De Schrijver TEGRA_REVISION_MAX,
3635874f36SPeter De Schrijver };
3735874f36SPeter De Schrijver
38bebf683bSKartik enum tegra_platform {
39bebf683bSKartik TEGRA_PLATFORM_SILICON = 0,
40bebf683bSKartik TEGRA_PLATFORM_QT,
41bebf683bSKartik TEGRA_PLATFORM_SYSTEM_FPGA,
42bebf683bSKartik TEGRA_PLATFORM_UNIT_FPGA,
43bebf683bSKartik TEGRA_PLATFORM_ASIM_QT,
44bebf683bSKartik TEGRA_PLATFORM_ASIM_LINSIM,
45bebf683bSKartik TEGRA_PLATFORM_DSIM_ASIM_LINSIM,
46bebf683bSKartik TEGRA_PLATFORM_VERIFICATION_SIMULATION,
47bebf683bSKartik TEGRA_PLATFORM_VDK,
48bebf683bSKartik TEGRA_PLATFORM_VSP,
49bebf683bSKartik TEGRA_PLATFORM_MAX,
50bebf683bSKartik };
51bebf683bSKartik
52783c8f4cSPeter De Schrijver struct tegra_sku_info {
53783c8f4cSPeter De Schrijver int sku_id;
54783c8f4cSPeter De Schrijver int cpu_process_id;
55783c8f4cSPeter De Schrijver int cpu_speedo_id;
56783c8f4cSPeter De Schrijver int cpu_speedo_value;
57783c8f4cSPeter De Schrijver int cpu_iddq_value;
5803b3f4c8SThierry Reding int soc_process_id;
59783c8f4cSPeter De Schrijver int soc_speedo_id;
600dc5a0d8SThierry Reding int soc_speedo_value;
61783c8f4cSPeter De Schrijver int gpu_process_id;
620dc5a0d8SThierry Reding int gpu_speedo_id;
63783c8f4cSPeter De Schrijver int gpu_speedo_value;
64783c8f4cSPeter De Schrijver enum tegra_revision revision;
65bebf683bSKartik enum tegra_platform platform;
66783c8f4cSPeter De Schrijver };
67783c8f4cSPeter De Schrijver
6830b44e81SDmitry Osipenko #ifdef CONFIG_ARCH_TEGRA
6930b44e81SDmitry Osipenko extern struct tegra_sku_info tegra_sku_info;
7035874f36SPeter De Schrijver u32 tegra_read_straps(void);
716ea2609aSMikko Perttunen u32 tegra_read_ram_code(void);
72783c8f4cSPeter De Schrijver int tegra_fuse_readl(unsigned long offset, u32 *value);
7345e93440SDmitry Osipenko u32 tegra_read_chipid(void);
7445e93440SDmitry Osipenko u8 tegra_get_chip_id(void);
7545e93440SDmitry Osipenko u8 tegra_get_platform(void);
7645e93440SDmitry Osipenko bool tegra_is_silicon(void);
7796765cc4SSumit Gupta int tegra194_miscreg_mask_serror(void);
78245157a3SDmitry Osipenko #else
79245157a3SDmitry Osipenko static struct tegra_sku_info tegra_sku_info __maybe_unused;
8030b44e81SDmitry Osipenko
tegra_read_straps(void)8130b44e81SDmitry Osipenko static inline u32 tegra_read_straps(void)
8230b44e81SDmitry Osipenko {
8330b44e81SDmitry Osipenko return 0;
8430b44e81SDmitry Osipenko }
8530b44e81SDmitry Osipenko
tegra_read_ram_code(void)8630b44e81SDmitry Osipenko static inline u32 tegra_read_ram_code(void)
8730b44e81SDmitry Osipenko {
8830b44e81SDmitry Osipenko return 0;
8930b44e81SDmitry Osipenko }
9030b44e81SDmitry Osipenko
tegra_fuse_readl(unsigned long offset,u32 * value)9130b44e81SDmitry Osipenko static inline int tegra_fuse_readl(unsigned long offset, u32 *value)
9230b44e81SDmitry Osipenko {
9330b44e81SDmitry Osipenko return -ENODEV;
9430b44e81SDmitry Osipenko }
9545e93440SDmitry Osipenko
tegra_read_chipid(void)9645e93440SDmitry Osipenko static inline u32 tegra_read_chipid(void)
9745e93440SDmitry Osipenko {
9845e93440SDmitry Osipenko return 0;
9945e93440SDmitry Osipenko }
10045e93440SDmitry Osipenko
tegra_get_chip_id(void)10145e93440SDmitry Osipenko static inline u8 tegra_get_chip_id(void)
10245e93440SDmitry Osipenko {
10345e93440SDmitry Osipenko return 0;
10445e93440SDmitry Osipenko }
10545e93440SDmitry Osipenko
tegra_get_platform(void)10645e93440SDmitry Osipenko static inline u8 tegra_get_platform(void)
10745e93440SDmitry Osipenko {
10845e93440SDmitry Osipenko return 0;
10945e93440SDmitry Osipenko }
11045e93440SDmitry Osipenko
tegra_is_silicon(void)11145e93440SDmitry Osipenko static inline bool tegra_is_silicon(void)
11245e93440SDmitry Osipenko {
11345e93440SDmitry Osipenko return false;
11445e93440SDmitry Osipenko }
11596765cc4SSumit Gupta
tegra194_miscreg_mask_serror(void)11696765cc4SSumit Gupta static inline int tegra194_miscreg_mask_serror(void)
11796765cc4SSumit Gupta {
11896765cc4SSumit Gupta return false;
11996765cc4SSumit Gupta }
120245157a3SDmitry Osipenko #endif
12135874f36SPeter De Schrijver
12227a0342aSThierry Reding struct device *tegra_soc_device_register(void);
12327a0342aSThierry Reding
124304664eaSThierry Reding #endif /* __ASSEMBLY__ */
125306a7f91SThierry Reding
126306a7f91SThierry Reding #endif /* __SOC_TEGRA_FUSE_H__ */
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