Searched hist:"94 bf2658" (Results 1 – 4 of 4) sorted by relevance
/openbmc/qemu/target/ppc/ |
H A D | mem_helper.c | 94bf2658 Tue Jun 26 11:19:10 CDT 2018 Richard Henderson <richard.henderson@linaro.org> target/ppc: Use atomic load for LQ and LQARX Section 1.4 of the Power ISA v3.0B states that both of these instructions are single-copy atomic. As we cannot (yet) issue 128-bit loads within TCG, use the generic helpers provided. Since TCG cannot (yet) return a 128-bit value, add a slot within CPUPPCState for returning the high half of a 128-bit return value. This solution is preferred to the helper assigning to architectural registers directly, as it avoids clobbering all TCG live values. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
|
H A D | helper.h | 94bf2658 Tue Jun 26 11:19:10 CDT 2018 Richard Henderson <richard.henderson@linaro.org> target/ppc: Use atomic load for LQ and LQARX Section 1.4 of the Power ISA v3.0B states that both of these instructions are single-copy atomic. As we cannot (yet) issue 128-bit loads within TCG, use the generic helpers provided. Since TCG cannot (yet) return a 128-bit value, add a slot within CPUPPCState for returning the high half of a 128-bit return value. This solution is preferred to the helper assigning to architectural registers directly, as it avoids clobbering all TCG live values. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
|
H A D | translate.c | 94bf2658 Tue Jun 26 11:19:10 CDT 2018 Richard Henderson <richard.henderson@linaro.org> target/ppc: Use atomic load for LQ and LQARX Section 1.4 of the Power ISA v3.0B states that both of these instructions are single-copy atomic. As we cannot (yet) issue 128-bit loads within TCG, use the generic helpers provided. Since TCG cannot (yet) return a 128-bit value, add a slot within CPUPPCState for returning the high half of a 128-bit return value. This solution is preferred to the helper assigning to architectural registers directly, as it avoids clobbering all TCG live values. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
|
H A D | cpu.h | 94bf2658 Tue Jun 26 11:19:10 CDT 2018 Richard Henderson <richard.henderson@linaro.org> target/ppc: Use atomic load for LQ and LQARX Section 1.4 of the Power ISA v3.0B states that both of these instructions are single-copy atomic. As we cannot (yet) issue 128-bit loads within TCG, use the generic helpers provided. Since TCG cannot (yet) return a 128-bit value, add a slot within CPUPPCState for returning the high half of a 128-bit return value. This solution is preferred to the helper assigning to architectural registers directly, as it avoids clobbering all TCG live values. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
|