Searched hist:"91 f3bf0d" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | at91.h | 91f3bf0d Thu Nov 19 09:43:17 CST 2020 Claudiu Beznea <claudiu.beznea@microchip.com> clk: at91: sama7g5: register cpu clock
Register CPU clock as being the master clock prescaler. This would
be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider
between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the
frequencies supported by SAMA7G5 could be directly received from
CPUPLL + master clock prescaler and the extra divider would do no work in
case it would be enabled.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-12-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
|
| /openbmc/linux/drivers/clk/at91/ |
| H A D | sama7g5.c | 91f3bf0d Thu Nov 19 09:43:17 CST 2020 Claudiu Beznea <claudiu.beznea@microchip.com> clk: at91: sama7g5: register cpu clock
Register CPU clock as being the master clock prescaler. This would
be used by DVFS. The block schema of SAMA7G5's PMC contains also a divider
between master clock prescaler and CPU (PMC_CPU_RATIO.RATIO) but the
frequencies supported by SAMA7G5 could be directly received from
CPUPLL + master clock prescaler and the extra divider would do no work in
case it would be enabled.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-12-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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