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H A D | tegra210-car.h | 88893986 Mon Dec 21 15:17:31 CST 2020 Sowjanya Komatineni <skomatineni@nvidia.com> dt-bindings: clock: tegra: Add clock ID TEGRA210_CLK_QSPI_PM
Tegra210 QSPI clock output has divider DIV2_SEL which will be enabled when using DDR interface mode.
This patch adds clock ID for this to dt-binding.
Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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