Searched hist:"862 e2e75" (Results 1 – 4 of 4) sorted by relevance
| /openbmc/u-boot/configs/ |
| H A D | qemu-riscv64_defconfig | 862e2e75 Thu Nov 22 04:26:12 CST 2018 Lukas Auer <lukas.auer@aisec.fraunhofer.de> riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I
RISC-V defines the base integer instruction sets as RV32I and RV64I.
Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to
match this convention.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
|
| /openbmc/u-boot/arch/riscv/lib/ |
| H A D | setjmp.S | 862e2e75 Thu Nov 22 04:26:12 CST 2018 Lukas Auer <lukas.auer@aisec.fraunhofer.de> riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I
RISC-V defines the base integer instruction sets as RV32I and RV64I.
Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to
match this convention.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
|
| /openbmc/u-boot/arch/riscv/ |
| H A D | Kconfig | 862e2e75 Thu Nov 22 04:26:12 CST 2018 Lukas Auer <lukas.auer@aisec.fraunhofer.de> riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I
RISC-V defines the base integer instruction sets as RV32I and RV64I.
Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to
match this convention.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
|
| /openbmc/u-boot/include/ |
| H A D | config_distro_bootcmd.h | 862e2e75 Thu Nov 22 04:26:12 CST 2018 Lukas Auer <lukas.auer@aisec.fraunhofer.de> riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I
RISC-V defines the base integer instruction sets as RV32I and RV64I.
Rename CPU_RISCV_32 and CPU_RISCV_64 to ARCH_RV32I and ARCH_RV64I to
match this convention.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
|