Searched hist:"854 cace6" (Results 1 – 3 of 3) sorted by relevance
| /openbmc/linux/drivers/net/ethernet/wangxun/ |
| H A D | Kconfig | 854cace6 Tue Jun 06 04:21:06 CDT 2023 Jiawen Wu <jiawenwu@trustnetic.com> net: txgbe: Implement phylink pcs
Register MDIO bus for PCS layer to use Synopsys designware XPCS, support
10GBASE-R interface to the controller.
Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
|
| /openbmc/linux/drivers/net/ethernet/wangxun/txgbe/ |
| H A D | txgbe_phy.c | 854cace6 Tue Jun 06 04:21:06 CDT 2023 Jiawen Wu <jiawenwu@trustnetic.com> net: txgbe: Implement phylink pcs
Register MDIO bus for PCS layer to use Synopsys designware XPCS, support
10GBASE-R interface to the controller.
Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
|
| H A D | txgbe_type.h | 854cace6 Tue Jun 06 04:21:06 CDT 2023 Jiawen Wu <jiawenwu@trustnetic.com> net: txgbe: Implement phylink pcs
Register MDIO bus for PCS layer to use Synopsys designware XPCS, support
10GBASE-R interface to the controller.
Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Maciej Fijalkowski <maciej.fijalkowski@intel.com>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
|