13ce7547eSJiawen Wu /* SPDX-License-Identifier: GPL-2.0 */
23ce7547eSJiawen Wu /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */
33ce7547eSJiawen Wu
43ce7547eSJiawen Wu #ifndef _TXGBE_TYPE_H_
53ce7547eSJiawen Wu #define _TXGBE_TYPE_H_
63ce7547eSJiawen Wu
7c3e382adSJiawen Wu #include <linux/property.h>
8c3e382adSJiawen Wu
93ce7547eSJiawen Wu /* Device IDs */
103ce7547eSJiawen Wu #define TXGBE_DEV_ID_SP1000 0x1001
113ce7547eSJiawen Wu #define TXGBE_DEV_ID_WX1820 0x2001
123ce7547eSJiawen Wu
133ce7547eSJiawen Wu /* Subsystem IDs */
143ce7547eSJiawen Wu /* SFP */
153ce7547eSJiawen Wu #define TXGBE_ID_SP1000_SFP 0x0000
163ce7547eSJiawen Wu #define TXGBE_ID_WX1820_SFP 0x2000
173ce7547eSJiawen Wu #define TXGBE_ID_SFP 0x00
183ce7547eSJiawen Wu
193ce7547eSJiawen Wu /* copper */
203ce7547eSJiawen Wu #define TXGBE_ID_SP1000_XAUI 0x1010
213ce7547eSJiawen Wu #define TXGBE_ID_WX1820_XAUI 0x2010
223ce7547eSJiawen Wu #define TXGBE_ID_XAUI 0x10
233ce7547eSJiawen Wu #define TXGBE_ID_SP1000_SGMII 0x1020
243ce7547eSJiawen Wu #define TXGBE_ID_WX1820_SGMII 0x2020
253ce7547eSJiawen Wu #define TXGBE_ID_SGMII 0x20
263ce7547eSJiawen Wu /* backplane */
273ce7547eSJiawen Wu #define TXGBE_ID_SP1000_KR_KX_KX4 0x1030
283ce7547eSJiawen Wu #define TXGBE_ID_WX1820_KR_KX_KX4 0x2030
293ce7547eSJiawen Wu #define TXGBE_ID_KR_KX_KX4 0x30
303ce7547eSJiawen Wu /* MAC Interface */
313ce7547eSJiawen Wu #define TXGBE_ID_SP1000_MAC_XAUI 0x1040
323ce7547eSJiawen Wu #define TXGBE_ID_WX1820_MAC_XAUI 0x2040
333ce7547eSJiawen Wu #define TXGBE_ID_MAC_XAUI 0x40
343ce7547eSJiawen Wu #define TXGBE_ID_SP1000_MAC_SGMII 0x1060
353ce7547eSJiawen Wu #define TXGBE_ID_WX1820_MAC_SGMII 0x2060
363ce7547eSJiawen Wu #define TXGBE_ID_MAC_SGMII 0x60
373ce7547eSJiawen Wu
383ce7547eSJiawen Wu /* Combined interface*/
393ce7547eSJiawen Wu #define TXGBE_ID_SFI_XAUI 0x50
403ce7547eSJiawen Wu
413ce7547eSJiawen Wu /* Revision ID */
423ce7547eSJiawen Wu #define TXGBE_SP_MPW 1
433ce7547eSJiawen Wu
44a34b3e6eSJiawen Wu /**************** SP Registers ****************************/
45d21d2c7fSJiawen Wu /* chip control Registers */
46d21d2c7fSJiawen Wu #define TXGBE_MIS_PRB_CTL 0x10010
47d21d2c7fSJiawen Wu #define TXGBE_MIS_PRB_CTL_LAN_UP(_i) BIT(1 - (_i))
48a34b3e6eSJiawen Wu /* FMGR Registers */
49a34b3e6eSJiawen Wu #define TXGBE_SPI_ILDR_STATUS 0x10120
50a34b3e6eSJiawen Wu #define TXGBE_SPI_ILDR_STATUS_PERST BIT(0) /* PCIE_PERST is done */
51a34b3e6eSJiawen Wu #define TXGBE_SPI_ILDR_STATUS_PWRRST BIT(1) /* Power on reset is done */
52b0801256SJiawen Wu #define TXGBE_SPI_ILDR_STATUS_LAN_SW_RST(_i) BIT((_i) + 9) /* lan soft reset done */
53b0801256SJiawen Wu
54b0801256SJiawen Wu /* Sensors for PVT(Process Voltage Temperature) */
55b0801256SJiawen Wu #define TXGBE_TS_CTL 0x10300
56b0801256SJiawen Wu #define TXGBE_TS_CTL_EVAL_MD BIT(31)
57a34b3e6eSJiawen Wu
58b83c3731SJiawen Wu /* GPIO register bit */
59b83c3731SJiawen Wu #define TXGBE_GPIOBIT_0 BIT(0) /* I:tx fault */
60b83c3731SJiawen Wu #define TXGBE_GPIOBIT_1 BIT(1) /* O:tx disabled */
61b83c3731SJiawen Wu #define TXGBE_GPIOBIT_2 BIT(2) /* I:sfp module absent */
62b83c3731SJiawen Wu #define TXGBE_GPIOBIT_3 BIT(3) /* I:rx signal lost */
63b83c3731SJiawen Wu #define TXGBE_GPIOBIT_4 BIT(4) /* O:rate select, 1G(0) 10G(1) */
64b83c3731SJiawen Wu #define TXGBE_GPIOBIT_5 BIT(5) /* O:rate select, 1G(0) 10G(1) */
65b83c3731SJiawen Wu
66b83c3731SJiawen Wu /* Extended Interrupt Enable Set */
67b83c3731SJiawen Wu #define TXGBE_PX_MISC_ETH_LKDN BIT(8)
68b83c3731SJiawen Wu #define TXGBE_PX_MISC_DEV_RST BIT(10)
69b83c3731SJiawen Wu #define TXGBE_PX_MISC_ETH_EVENT BIT(17)
70b83c3731SJiawen Wu #define TXGBE_PX_MISC_ETH_LK BIT(18)
71b83c3731SJiawen Wu #define TXGBE_PX_MISC_ETH_AN BIT(19)
72b83c3731SJiawen Wu #define TXGBE_PX_MISC_INT_ERR BIT(20)
73b83c3731SJiawen Wu #define TXGBE_PX_MISC_GPIO BIT(26)
74b83c3731SJiawen Wu #define TXGBE_PX_MISC_IEN_MASK \
75b83c3731SJiawen Wu (TXGBE_PX_MISC_ETH_LKDN | TXGBE_PX_MISC_DEV_RST | \
76b83c3731SJiawen Wu TXGBE_PX_MISC_ETH_EVENT | TXGBE_PX_MISC_ETH_LK | \
77b83c3731SJiawen Wu TXGBE_PX_MISC_ETH_AN | TXGBE_PX_MISC_INT_ERR | \
78b83c3731SJiawen Wu TXGBE_PX_MISC_GPIO)
79b83c3731SJiawen Wu
80*08f08f93SJiawen Wu /* Port cfg registers */
81*08f08f93SJiawen Wu #define TXGBE_CFG_PORT_ST 0x14404
82*08f08f93SJiawen Wu #define TXGBE_CFG_PORT_ST_LINK_UP BIT(0)
83*08f08f93SJiawen Wu
84c625e725SJiawen Wu /* I2C registers */
85c625e725SJiawen Wu #define TXGBE_I2C_BASE 0x14900
86c625e725SJiawen Wu
87854cace6SJiawen Wu /************************************** ETH PHY ******************************/
88854cace6SJiawen Wu #define TXGBE_XPCS_IDA_ADDR 0x13000
89854cace6SJiawen Wu #define TXGBE_XPCS_IDA_DATA 0x13004
90854cace6SJiawen Wu
91049fe536SJiawen Wu /* Part Number String Length */
92049fe536SJiawen Wu #define TXGBE_PBANUM_LENGTH 32
93049fe536SJiawen Wu
94049fe536SJiawen Wu /* Checksum and EEPROM pointers */
95049fe536SJiawen Wu #define TXGBE_EEPROM_LAST_WORD 0x800
96049fe536SJiawen Wu #define TXGBE_EEPROM_CHECKSUM 0x2F
97049fe536SJiawen Wu #define TXGBE_EEPROM_SUM 0xBABA
98049fe536SJiawen Wu #define TXGBE_EEPROM_VERSION_L 0x1D
99049fe536SJiawen Wu #define TXGBE_EEPROM_VERSION_H 0x1E
100049fe536SJiawen Wu #define TXGBE_ISCSI_BOOT_CONFIG 0x07
101049fe536SJiawen Wu #define TXGBE_PBANUM0_PTR 0x05
102049fe536SJiawen Wu #define TXGBE_PBANUM1_PTR 0x06
103049fe536SJiawen Wu #define TXGBE_PBANUM_PTR_GUARD 0xFAFA
104049fe536SJiawen Wu
1055d3ac705SJiawen Wu #define TXGBE_MAX_MSIX_VECTORS 64
106524f6b29SJiawen Wu #define TXGBE_MAX_FDIR_INDICES 63
107524f6b29SJiawen Wu
108524f6b29SJiawen Wu #define TXGBE_MAX_RX_QUEUES (TXGBE_MAX_FDIR_INDICES + 1)
109524f6b29SJiawen Wu #define TXGBE_MAX_TX_QUEUES (TXGBE_MAX_FDIR_INDICES + 1)
110524f6b29SJiawen Wu
111524f6b29SJiawen Wu #define TXGBE_SP_MAX_TX_QUEUES 128
112524f6b29SJiawen Wu #define TXGBE_SP_MAX_RX_QUEUES 128
113524f6b29SJiawen Wu #define TXGBE_SP_RAR_ENTRIES 128
114524f6b29SJiawen Wu #define TXGBE_SP_MC_TBL_SIZE 128
1157df4af51SMengyuan Lou #define TXGBE_SP_VFT_TBL_SIZE 128
1160ef7e159SJiawen Wu #define TXGBE_SP_RX_PB_SIZE 512
1170ef7e159SJiawen Wu #define TXGBE_SP_TDB_PB_SZ (160 * 1024) /* 160KB Packet Buffer */
118524f6b29SJiawen Wu
1195d3ac705SJiawen Wu /* TX/RX descriptor defines */
1205d3ac705SJiawen Wu #define TXGBE_DEFAULT_TXD 512
1215d3ac705SJiawen Wu #define TXGBE_DEFAULT_TX_WORK 256
1225d3ac705SJiawen Wu
1235d3ac705SJiawen Wu #if (PAGE_SIZE < 8192)
1245d3ac705SJiawen Wu #define TXGBE_DEFAULT_RXD 512
1255d3ac705SJiawen Wu #define TXGBE_DEFAULT_RX_WORK 256
1265d3ac705SJiawen Wu #else
1275d3ac705SJiawen Wu #define TXGBE_DEFAULT_RXD 256
1285d3ac705SJiawen Wu #define TXGBE_DEFAULT_RX_WORK 128
1295d3ac705SJiawen Wu #endif
1305d3ac705SJiawen Wu
1315d3ac705SJiawen Wu #define TXGBE_INTR_MISC(A) BIT((A)->num_q_vectors)
1325d3ac705SJiawen Wu #define TXGBE_INTR_QALL(A) (TXGBE_INTR_MISC(A) - 1)
1335d3ac705SJiawen Wu
1345d3ac705SJiawen Wu #define TXGBE_MAX_EITR GENMASK(11, 3)
1355d3ac705SJiawen Wu
136524f6b29SJiawen Wu extern char txgbe_driver_name[];
137524f6b29SJiawen Wu
netdev_to_txgbe(struct net_device * netdev)138c3e382adSJiawen Wu static inline struct txgbe *netdev_to_txgbe(struct net_device *netdev)
139c3e382adSJiawen Wu {
140c3e382adSJiawen Wu struct wx *wx = netdev_priv(netdev);
141c3e382adSJiawen Wu
142c3e382adSJiawen Wu return wx->priv;
143c3e382adSJiawen Wu }
144c3e382adSJiawen Wu
145c3e382adSJiawen Wu #define NODE_PROP(_NAME, _PROP) \
146c3e382adSJiawen Wu (const struct software_node) { \
147c3e382adSJiawen Wu .name = _NAME, \
148c3e382adSJiawen Wu .properties = _PROP, \
149c3e382adSJiawen Wu }
150c3e382adSJiawen Wu
151c3e382adSJiawen Wu enum txgbe_swnodes {
152c3e382adSJiawen Wu SWNODE_GPIO = 0,
153c3e382adSJiawen Wu SWNODE_I2C,
154c3e382adSJiawen Wu SWNODE_SFP,
155c3e382adSJiawen Wu SWNODE_PHYLINK,
156c3e382adSJiawen Wu SWNODE_MAX
157c3e382adSJiawen Wu };
158c3e382adSJiawen Wu
159c3e382adSJiawen Wu struct txgbe_nodes {
160c3e382adSJiawen Wu char gpio_name[32];
161c3e382adSJiawen Wu char i2c_name[32];
162c3e382adSJiawen Wu char sfp_name[32];
163c3e382adSJiawen Wu char phylink_name[32];
164c3e382adSJiawen Wu struct property_entry gpio_props[1];
165c3e382adSJiawen Wu struct property_entry i2c_props[3];
166c3e382adSJiawen Wu struct property_entry sfp_props[8];
167c3e382adSJiawen Wu struct property_entry phylink_props[2];
168c3e382adSJiawen Wu struct software_node_ref_args i2c_ref[1];
169c3e382adSJiawen Wu struct software_node_ref_args gpio0_ref[1];
170c3e382adSJiawen Wu struct software_node_ref_args gpio1_ref[1];
171c3e382adSJiawen Wu struct software_node_ref_args gpio2_ref[1];
172c3e382adSJiawen Wu struct software_node_ref_args gpio3_ref[1];
173c3e382adSJiawen Wu struct software_node_ref_args gpio4_ref[1];
174c3e382adSJiawen Wu struct software_node_ref_args gpio5_ref[1];
175c3e382adSJiawen Wu struct software_node_ref_args sfp_ref[1];
176c3e382adSJiawen Wu struct software_node swnodes[SWNODE_MAX];
177c3e382adSJiawen Wu const struct software_node *group[SWNODE_MAX + 1];
178c3e382adSJiawen Wu };
179c3e382adSJiawen Wu
180c3e382adSJiawen Wu struct txgbe {
181c3e382adSJiawen Wu struct wx *wx;
182c3e382adSJiawen Wu struct txgbe_nodes nodes;
183854cace6SJiawen Wu struct dw_xpcs *xpcs;
184*08f08f93SJiawen Wu struct phylink *phylink;
18504d94236SJiawen Wu struct platform_device *sfp_dev;
186c625e725SJiawen Wu struct platform_device *i2c_dev;
187b63f2048SJiawen Wu struct clk_lookup *clock;
188b63f2048SJiawen Wu struct clk *clk;
189b83c3731SJiawen Wu struct gpio_chip *gpio;
190c3e382adSJiawen Wu };
191c3e382adSJiawen Wu
1923ce7547eSJiawen Wu #endif /* _TXGBE_TYPE_H_ */
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