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| /openbmc/u-boot/drivers/clk/ |
| H A D | clk_stm32f.c | 651a70e8 Thu Feb 08 10:20:47 CST 2018 Patrice Chotard <patrice.chotard@st.com> clk: clk_stm32f: No more need of 48Mhz from PLL_SAI
Initially, 48Mhz for SDIO clock was generated from SAI pll for
STM32F469 and STM32F746 SoCs, but this solution was not suitable
for STM32F429 SoCs.
A generic solution is to used the PLL_Q output as 48Mhz clock
for all STM32F SOCs family.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
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