Searched hist:"64501 c669851e45dd47699349dae6b5798c075a3" (Results 1 – 6 of 6) sorted by relevance
/openbmc/u-boot/board/freescale/bsc9132qds/ |
H A D | law.c | 64501c669851e45dd47699349dae6b5798c075a3 Mon Jul 01 22:51:04 CDT 2013 Priyanka Jain <Priyanka.Jain@freescale.com> board/bsc9132qds: Add DSP side tlb and laws
BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a integrated device that contains two powerpc e500v2 cores and two DSP starcores.
To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 and M3 memory -Creating LAW for 1GB DDR which is connected exclusively to DSP-cores
Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
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H A D | tlb.c | 64501c669851e45dd47699349dae6b5798c075a3 Mon Jul 01 22:51:04 CDT 2013 Priyanka Jain <Priyanka.Jain@freescale.com> board/bsc9132qds: Add DSP side tlb and laws
BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a integrated device that contains two powerpc e500v2 cores and two DSP starcores.
To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 and M3 memory -Creating LAW for 1GB DDR which is connected exclusively to DSP-cores
Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
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/openbmc/u-boot/arch/powerpc/include/asm/ |
H A D | fsl_law.h | 64501c669851e45dd47699349dae6b5798c075a3 Mon Jul 01 22:51:04 CDT 2013 Priyanka Jain <Priyanka.Jain@freescale.com> board/bsc9132qds: Add DSP side tlb and laws
BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a integrated device that contains two powerpc e500v2 cores and two DSP starcores.
To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 and M3 memory -Creating LAW for 1GB DDR which is connected exclusively to DSP-cores
Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
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H A D | config_mpc85xx.h | 64501c669851e45dd47699349dae6b5798c075a3 Mon Jul 01 22:51:04 CDT 2013 Priyanka Jain <Priyanka.Jain@freescale.com> board/bsc9132qds: Add DSP side tlb and laws
BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a integrated device that contains two powerpc e500v2 cores and two DSP starcores.
To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 and M3 memory -Creating LAW for 1GB DDR which is connected exclusively to DSP-cores
Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
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/openbmc/u-boot/include/configs/ |
H A D | BSC9132QDS.h | 64501c669851e45dd47699349dae6b5798c075a3 Mon Jul 01 22:51:04 CDT 2013 Priyanka Jain <Priyanka.Jain@freescale.com> board/bsc9132qds: Add DSP side tlb and laws
BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a integrated device that contains two powerpc e500v2 cores and two DSP starcores.
To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 and M3 memory -Creating LAW for 1GB DDR which is connected exclusively to DSP-cores
Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
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/openbmc/u-boot/ |
H A D | README | 64501c669851e45dd47699349dae6b5798c075a3 Mon Jul 01 22:51:04 CDT 2013 Priyanka Jain <Priyanka.Jain@freescale.com> board/bsc9132qds: Add DSP side tlb and laws
BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a integrated device that contains two powerpc e500v2 cores and two DSP starcores.
To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 and M3 memory -Creating LAW for 1GB DDR which is connected exclusively to DSP-cores
Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
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