| /openbmc/linux/arch/arm64/boot/dts/ti/ |
| H A D | k3-am62a.dtsi | 5fc6b1b6 Thu Sep 01 09:13:27 CDT 2022 Vignesh Raghavendra <vigneshr@ti.com> arm64: dts: ti: Introduce AM62A7 family of SoCs
The AM62A SoC belongs to the K3 Multicore SoC architecture platform that
can run edge AI applications with Video/Vision processing. This provides
advanced system integration with high security support to enable a broad
set of applications in industrial/automotive markets such as, driver
monitoring, machine vision, smart camera, eMirror, front camera,
robotics, and building automation.
Some highlights of AM62A SoC are:
* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single
core variants are provided in the same package to allow HW compatible
designs.
* One Device manager Cortex-R5F for system power and resource management, and
one Cortex-R5F for Functional Safety or general-purpose usage.
* One AI accelerator (up to 2 TOPS), using one C7x256V DSP w/Matrix Multiplier
accelerator (MMA) for Deep Learning usage.
* VPAC3L(Vision Pre-processing Accelerator), providing 12-bit ISP up to
315MPixel/s RGB+IR support, and Noise Filter for improved integrated imaging
and vision image processing.
* H.264/H.265 Video Encode/Decode. + Motion JPEG encode
* Display support, providing 24-bit RBG parallel interface up to 200MHz pixel
clock support for 2K display resolution.
* Integrated Giga-bit Ethernet switch supporting up to a total of two external
ports (TSN capable).
* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA
connection, OSPI memory controller, 3x McASP for audio, 1x CSI-RX-4L for
Camera, eCAP/eQEP, ePWM, among other peripherals.
* Dedicated Centralized Hardware Security Module with support for secure boot,
debug security and crypto acceleration and trusted execution environment
* One 32 bit DDR Subsystem that supports LPDDR4, DDR4 memory types.
* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, enabling
battery powered system design.
More details about the SoCs can be found in the Technical Reference Manual:
https://www.ti.com/lit/zip/spruj16
Co-developed-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Devarsh Thakkar <devarsht@ti.com>
Link: https://lore.kernel.org/r/20220901141328.899100-5-vigneshr@ti.com
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| H A D | k3-am62a7.dtsi | 5fc6b1b6 Thu Sep 01 09:13:27 CDT 2022 Vignesh Raghavendra <vigneshr@ti.com> arm64: dts: ti: Introduce AM62A7 family of SoCs
The AM62A SoC belongs to the K3 Multicore SoC architecture platform that
can run edge AI applications with Video/Vision processing. This provides
advanced system integration with high security support to enable a broad
set of applications in industrial/automotive markets such as, driver
monitoring, machine vision, smart camera, eMirror, front camera,
robotics, and building automation.
Some highlights of AM62A SoC are:
* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single
core variants are provided in the same package to allow HW compatible
designs.
* One Device manager Cortex-R5F for system power and resource management, and
one Cortex-R5F for Functional Safety or general-purpose usage.
* One AI accelerator (up to 2 TOPS), using one C7x256V DSP w/Matrix Multiplier
accelerator (MMA) for Deep Learning usage.
* VPAC3L(Vision Pre-processing Accelerator), providing 12-bit ISP up to
315MPixel/s RGB+IR support, and Noise Filter for improved integrated imaging
and vision image processing.
* H.264/H.265 Video Encode/Decode. + Motion JPEG encode
* Display support, providing 24-bit RBG parallel interface up to 200MHz pixel
clock support for 2K display resolution.
* Integrated Giga-bit Ethernet switch supporting up to a total of two external
ports (TSN capable).
* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA
connection, OSPI memory controller, 3x McASP for audio, 1x CSI-RX-4L for
Camera, eCAP/eQEP, ePWM, among other peripherals.
* Dedicated Centralized Hardware Security Module with support for secure boot,
debug security and crypto acceleration and trusted execution environment
* One 32 bit DDR Subsystem that supports LPDDR4, DDR4 memory types.
* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, enabling
battery powered system design.
More details about the SoCs can be found in the Technical Reference Manual:
https://www.ti.com/lit/zip/spruj16
Co-developed-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Devarsh Thakkar <devarsht@ti.com>
Link: https://lore.kernel.org/r/20220901141328.899100-5-vigneshr@ti.com
|
| H A D | k3-am62a-wakeup.dtsi | 5fc6b1b6 Thu Sep 01 09:13:27 CDT 2022 Vignesh Raghavendra <vigneshr@ti.com> arm64: dts: ti: Introduce AM62A7 family of SoCs
The AM62A SoC belongs to the K3 Multicore SoC architecture platform that
can run edge AI applications with Video/Vision processing. This provides
advanced system integration with high security support to enable a broad
set of applications in industrial/automotive markets such as, driver
monitoring, machine vision, smart camera, eMirror, front camera,
robotics, and building automation.
Some highlights of AM62A SoC are:
* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single
core variants are provided in the same package to allow HW compatible
designs.
* One Device manager Cortex-R5F for system power and resource management, and
one Cortex-R5F for Functional Safety or general-purpose usage.
* One AI accelerator (up to 2 TOPS), using one C7x256V DSP w/Matrix Multiplier
accelerator (MMA) for Deep Learning usage.
* VPAC3L(Vision Pre-processing Accelerator), providing 12-bit ISP up to
315MPixel/s RGB+IR support, and Noise Filter for improved integrated imaging
and vision image processing.
* H.264/H.265 Video Encode/Decode. + Motion JPEG encode
* Display support, providing 24-bit RBG parallel interface up to 200MHz pixel
clock support for 2K display resolution.
* Integrated Giga-bit Ethernet switch supporting up to a total of two external
ports (TSN capable).
* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA
connection, OSPI memory controller, 3x McASP for audio, 1x CSI-RX-4L for
Camera, eCAP/eQEP, ePWM, among other peripherals.
* Dedicated Centralized Hardware Security Module with support for secure boot,
debug security and crypto acceleration and trusted execution environment
* One 32 bit DDR Subsystem that supports LPDDR4, DDR4 memory types.
* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, enabling
battery powered system design.
More details about the SoCs can be found in the Technical Reference Manual:
https://www.ti.com/lit/zip/spruj16
Co-developed-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Devarsh Thakkar <devarsht@ti.com>
Link: https://lore.kernel.org/r/20220901141328.899100-5-vigneshr@ti.com
|
| H A D | k3-am62a-mcu.dtsi | 5fc6b1b6 Thu Sep 01 09:13:27 CDT 2022 Vignesh Raghavendra <vigneshr@ti.com> arm64: dts: ti: Introduce AM62A7 family of SoCs
The AM62A SoC belongs to the K3 Multicore SoC architecture platform that
can run edge AI applications with Video/Vision processing. This provides
advanced system integration with high security support to enable a broad
set of applications in industrial/automotive markets such as, driver
monitoring, machine vision, smart camera, eMirror, front camera,
robotics, and building automation.
Some highlights of AM62A SoC are:
* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single
core variants are provided in the same package to allow HW compatible
designs.
* One Device manager Cortex-R5F for system power and resource management, and
one Cortex-R5F for Functional Safety or general-purpose usage.
* One AI accelerator (up to 2 TOPS), using one C7x256V DSP w/Matrix Multiplier
accelerator (MMA) for Deep Learning usage.
* VPAC3L(Vision Pre-processing Accelerator), providing 12-bit ISP up to
315MPixel/s RGB+IR support, and Noise Filter for improved integrated imaging
and vision image processing.
* H.264/H.265 Video Encode/Decode. + Motion JPEG encode
* Display support, providing 24-bit RBG parallel interface up to 200MHz pixel
clock support for 2K display resolution.
* Integrated Giga-bit Ethernet switch supporting up to a total of two external
ports (TSN capable).
* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA
connection, OSPI memory controller, 3x McASP for audio, 1x CSI-RX-4L for
Camera, eCAP/eQEP, ePWM, among other peripherals.
* Dedicated Centralized Hardware Security Module with support for secure boot,
debug security and crypto acceleration and trusted execution environment
* One 32 bit DDR Subsystem that supports LPDDR4, DDR4 memory types.
* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, enabling
battery powered system design.
More details about the SoCs can be found in the Technical Reference Manual:
https://www.ti.com/lit/zip/spruj16
Co-developed-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Devarsh Thakkar <devarsht@ti.com>
Link: https://lore.kernel.org/r/20220901141328.899100-5-vigneshr@ti.com
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| H A D | k3-am62a-main.dtsi | 5fc6b1b6 Thu Sep 01 09:13:27 CDT 2022 Vignesh Raghavendra <vigneshr@ti.com> arm64: dts: ti: Introduce AM62A7 family of SoCs
The AM62A SoC belongs to the K3 Multicore SoC architecture platform that
can run edge AI applications with Video/Vision processing. This provides
advanced system integration with high security support to enable a broad
set of applications in industrial/automotive markets such as, driver
monitoring, machine vision, smart camera, eMirror, front camera,
robotics, and building automation.
Some highlights of AM62A SoC are:
* Quad-Cortex-A53s (running up to 1.4GHz) in a single cluster. Dual/Single
core variants are provided in the same package to allow HW compatible
designs.
* One Device manager Cortex-R5F for system power and resource management, and
one Cortex-R5F for Functional Safety or general-purpose usage.
* One AI accelerator (up to 2 TOPS), using one C7x256V DSP w/Matrix Multiplier
accelerator (MMA) for Deep Learning usage.
* VPAC3L(Vision Pre-processing Accelerator), providing 12-bit ISP up to
315MPixel/s RGB+IR support, and Noise Filter for improved integrated imaging
and vision image processing.
* H.264/H.265 Video Encode/Decode. + Motion JPEG encode
* Display support, providing 24-bit RBG parallel interface up to 200MHz pixel
clock support for 2K display resolution.
* Integrated Giga-bit Ethernet switch supporting up to a total of two external
ports (TSN capable).
* 9xUARTs, 5xSPI, 6xI2C, 2xUSB2, 3xCAN-FD, 3x eMMC and SD, GPMC for NAND/FPGA
connection, OSPI memory controller, 3x McASP for audio, 1x CSI-RX-4L for
Camera, eCAP/eQEP, ePWM, among other peripherals.
* Dedicated Centralized Hardware Security Module with support for secure boot,
debug security and crypto acceleration and trusted execution environment
* One 32 bit DDR Subsystem that supports LPDDR4, DDR4 memory types.
* Multiple low power modes support, ex: Deep sleep, Standby, MCU-only, enabling
battery powered system design.
More details about the SoCs can be found in the Technical Reference Manual:
https://www.ti.com/lit/zip/spruj16
Co-developed-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Bryan Brattlof <bb@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Devarsh Thakkar <devarsht@ti.com>
Link: https://lore.kernel.org/r/20220901141328.899100-5-vigneshr@ti.com
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