Searched hist:53499282 (Results 1 – 8 of 8) sorted by relevance
| /openbmc/u-boot/board/freescale/t4rdb/ |
| H A D | ddr.c | 53499282 Tue May 31 02:39:06 CDT 2016 Shengzhou Liu <Shengzhou.Liu@nxp.com> board/freescale: Use unified setup_ddr_tlbs for spl boot and non-spl boot
We should use unified setup_ddr_tlbs() for spl boot and non-spl boot
to make sure 'M' bit is set for DDR TLB to maintain cache coherence.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
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| /openbmc/u-boot/board/freescale/t208xqds/ |
| H A D | ddr.c | 53499282 Tue May 31 02:39:06 CDT 2016 Shengzhou Liu <Shengzhou.Liu@nxp.com> board/freescale: Use unified setup_ddr_tlbs for spl boot and non-spl boot
We should use unified setup_ddr_tlbs() for spl boot and non-spl boot
to make sure 'M' bit is set for DDR TLB to maintain cache coherence.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
|
| /openbmc/u-boot/board/freescale/t102xqds/ |
| H A D | ddr.c | 53499282 Tue May 31 02:39:06 CDT 2016 Shengzhou Liu <Shengzhou.Liu@nxp.com> board/freescale: Use unified setup_ddr_tlbs for spl boot and non-spl boot
We should use unified setup_ddr_tlbs() for spl boot and non-spl boot
to make sure 'M' bit is set for DDR TLB to maintain cache coherence.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
|
| /openbmc/u-boot/board/freescale/t208xrdb/ |
| H A D | ddr.c | 53499282 Tue May 31 02:39:06 CDT 2016 Shengzhou Liu <Shengzhou.Liu@nxp.com> board/freescale: Use unified setup_ddr_tlbs for spl boot and non-spl boot
We should use unified setup_ddr_tlbs() for spl boot and non-spl boot
to make sure 'M' bit is set for DDR TLB to maintain cache coherence.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
|
| /openbmc/u-boot/board/freescale/t102xrdb/ |
| H A D | ddr.c | 53499282 Tue May 31 02:39:06 CDT 2016 Shengzhou Liu <Shengzhou.Liu@nxp.com> board/freescale: Use unified setup_ddr_tlbs for spl boot and non-spl boot
We should use unified setup_ddr_tlbs() for spl boot and non-spl boot
to make sure 'M' bit is set for DDR TLB to maintain cache coherence.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
|
| /openbmc/u-boot/board/freescale/b4860qds/ |
| H A D | ddr.c | 53499282 Tue May 31 02:39:06 CDT 2016 Shengzhou Liu <Shengzhou.Liu@nxp.com> board/freescale: Use unified setup_ddr_tlbs for spl boot and non-spl boot
We should use unified setup_ddr_tlbs() for spl boot and non-spl boot
to make sure 'M' bit is set for DDR TLB to maintain cache coherence.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
|
| /openbmc/u-boot/board/freescale/t104xrdb/ |
| H A D | ddr.c | 53499282 Tue May 31 02:39:06 CDT 2016 Shengzhou Liu <Shengzhou.Liu@nxp.com> board/freescale: Use unified setup_ddr_tlbs for spl boot and non-spl boot
We should use unified setup_ddr_tlbs() for spl boot and non-spl boot
to make sure 'M' bit is set for DDR TLB to maintain cache coherence.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
|
| /openbmc/u-boot/board/freescale/t4qds/ |
| H A D | ddr.c | 53499282 Tue May 31 02:39:06 CDT 2016 Shengzhou Liu <Shengzhou.Liu@nxp.com> board/freescale: Use unified setup_ddr_tlbs for spl boot and non-spl boot
We should use unified setup_ddr_tlbs() for spl boot and non-spl boot
to make sure 'M' bit is set for DDR TLB to maintain cache coherence.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
|