Searched hist:"4 b65b6e7" (Results 1 – 1 of 1) sorted by relevance
| /openbmc/qemu/target/ppc/ |
| H A D | translate.c | 4b65b6e7 Tue Sep 06 07:55:22 CDT 2022 Víctor Colombo <victor.colombo@eldorado.org.br> target/ppc: Zero second doubleword of VSR registers for FPR insns
FPR register are mapped to the first doubleword of the VSR registers.
Since PowerISA v3.1, the second doubleword of the target register
must be zeroed for FP instructions.
This patch does it by writting 0 to the second dw everytime the
first dw is being written using set_fpr.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220906125523.38765-8-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
|