Searched hist:"495134 b7" (Results 1 – 3 of 3) sorted by relevance
/openbmc/qemu/hw/riscv/ |
H A D | sifive_e.c | 495134b7 Mon Jun 15 19:50:38 CDT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 Per the SiFive manual, all E/U series CPU cores' reset vector is at 0x1004. Update our codes to match the hardware. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1592268641-7478-3-git-send-email-bmeng.cn@gmail.com Message-Id: <1592268641-7478-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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H A D | sifive_u.c | 495134b7 Mon Jun 15 19:50:38 CDT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 Per the SiFive manual, all E/U series CPU cores' reset vector is at 0x1004. Update our codes to match the hardware. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1592268641-7478-3-git-send-email-bmeng.cn@gmail.com Message-Id: <1592268641-7478-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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/openbmc/qemu/target/riscv/ |
H A D | cpu.c | 495134b7 Mon Jun 15 19:50:38 CDT 2020 Bin Meng <bin.meng@windriver.com> hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004 Per the SiFive manual, all E/U series CPU cores' reset vector is at 0x1004. Update our codes to match the hardware. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1592268641-7478-3-git-send-email-bmeng.cn@gmail.com Message-Id: <1592268641-7478-3-git-send-email-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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