Searched hist:"45 be0cdb" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/arch/arm/mach-socfpga/ |
| H A D | core.h | 45be0cdb Tue Jun 02 21:14:02 CDT 2015 Dinh Nguyen <dinguyen@opensource.altera.com> ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10
Add boot_secondary implementation for the Arria10 platform. Bringing up
the secondary core on the Arria 10 platform is pretty similar to the
Cyclone/Arria 5 platform, with the exception of the following differences:
- Register offset to bringup CPU1 out of reset is different.
- The cpu1-start-addr for Arria10 contains an additional nibble.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
45be0cdb Tue Jun 02 21:14:02 CDT 2015 Dinh Nguyen <dinguyen@opensource.altera.com> ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10
Add boot_secondary implementation for the Arria10 platform. Bringing up
the secondary core on the Arria 10 platform is pretty similar to the
Cyclone/Arria 5 platform, with the exception of the following differences:
- Register offset to bringup CPU1 out of reset is different.
- The cpu1-start-addr for Arria10 contains an additional nibble.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
|
| H A D | platsmp.c | 45be0cdb Tue Jun 02 21:14:02 CDT 2015 Dinh Nguyen <dinguyen@opensource.altera.com> ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10
Add boot_secondary implementation for the Arria10 platform. Bringing up
the secondary core on the Arria 10 platform is pretty similar to the
Cyclone/Arria 5 platform, with the exception of the following differences:
- Register offset to bringup CPU1 out of reset is different.
- The cpu1-start-addr for Arria10 contains an additional nibble.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
45be0cdb Tue Jun 02 21:14:02 CDT 2015 Dinh Nguyen <dinguyen@opensource.altera.com> ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10
Add boot_secondary implementation for the Arria10 platform. Bringing up
the secondary core on the Arria 10 platform is pretty similar to the
Cyclone/Arria 5 platform, with the exception of the following differences:
- Register offset to bringup CPU1 out of reset is different.
- The cpu1-start-addr for Arria10 contains an additional nibble.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
|