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/openbmc/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl/
H A Dhw_atl_b0.h40f05e5b Fri May 22 03:19:48 CDT 2020 Mark Starovoytov <mstarovoitov@marvell.com> net: atlantic: proper rss_ctrl1 (54c0) initialization

This patch fixes an inconsistency between code and spec, which
was found while working on the QoS implementation.

When 8TCs are used, 2 is the maximum supported number of index bits.
In a 4TC mode, we do support 3, but we shouldn't really use the bytes,
which are intended for the 8TC mode.

Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
40f05e5b Fri May 22 03:19:48 CDT 2020 Mark Starovoytov <mstarovoitov@marvell.com> net: atlantic: proper rss_ctrl1 (54c0) initialization

This patch fixes an inconsistency between code and spec, which
was found while working on the QoS implementation.

When 8TCs are used, 2 is the maximum supported number of index bits.
In a 4TC mode, we do support 3, but we shouldn't really use the bytes,
which are intended for the 8TC mode.

Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
H A Dhw_atl_b0_internal.h40f05e5b Fri May 22 03:19:48 CDT 2020 Mark Starovoytov <mstarovoitov@marvell.com> net: atlantic: proper rss_ctrl1 (54c0) initialization

This patch fixes an inconsistency between code and spec, which
was found while working on the QoS implementation.

When 8TCs are used, 2 is the maximum supported number of index bits.
In a 4TC mode, we do support 3, but we shouldn't really use the bytes,
which are intended for the 8TC mode.

Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
40f05e5b Fri May 22 03:19:48 CDT 2020 Mark Starovoytov <mstarovoitov@marvell.com> net: atlantic: proper rss_ctrl1 (54c0) initialization

This patch fixes an inconsistency between code and spec, which
was found while working on the QoS implementation.

When 8TCs are used, 2 is the maximum supported number of index bits.
In a 4TC mode, we do support 3, but we shouldn't really use the bytes,
which are intended for the 8TC mode.

Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
H A Dhw_atl_b0.c40f05e5b Fri May 22 03:19:48 CDT 2020 Mark Starovoytov <mstarovoitov@marvell.com> net: atlantic: proper rss_ctrl1 (54c0) initialization

This patch fixes an inconsistency between code and spec, which
was found while working on the QoS implementation.

When 8TCs are used, 2 is the maximum supported number of index bits.
In a 4TC mode, we do support 3, but we shouldn't really use the bytes,
which are intended for the 8TC mode.

Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
40f05e5b Fri May 22 03:19:48 CDT 2020 Mark Starovoytov <mstarovoitov@marvell.com> net: atlantic: proper rss_ctrl1 (54c0) initialization

This patch fixes an inconsistency between code and spec, which
was found while working on the QoS implementation.

When 8TCs are used, 2 is the maximum supported number of index bits.
In a 4TC mode, we do support 3, but we shouldn't really use the bytes,
which are intended for the 8TC mode.

Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
/openbmc/linux/drivers/net/ethernet/aquantia/atlantic/hw_atl2/
H A Dhw_atl2_internal.h40f05e5b Fri May 22 03:19:48 CDT 2020 Mark Starovoytov <mstarovoitov@marvell.com> net: atlantic: proper rss_ctrl1 (54c0) initialization

This patch fixes an inconsistency between code and spec, which
was found while working on the QoS implementation.

When 8TCs are used, 2 is the maximum supported number of index bits.
In a 4TC mode, we do support 3, but we shouldn't really use the bytes,
which are intended for the 8TC mode.

Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
40f05e5b Fri May 22 03:19:48 CDT 2020 Mark Starovoytov <mstarovoitov@marvell.com> net: atlantic: proper rss_ctrl1 (54c0) initialization

This patch fixes an inconsistency between code and spec, which
was found while working on the QoS implementation.

When 8TCs are used, 2 is the maximum supported number of index bits.
In a 4TC mode, we do support 3, but we shouldn't really use the bytes,
which are intended for the 8TC mode.

Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
H A Dhw_atl2.c40f05e5b Fri May 22 03:19:48 CDT 2020 Mark Starovoytov <mstarovoitov@marvell.com> net: atlantic: proper rss_ctrl1 (54c0) initialization

This patch fixes an inconsistency between code and spec, which
was found while working on the QoS implementation.

When 8TCs are used, 2 is the maximum supported number of index bits.
In a 4TC mode, we do support 3, but we shouldn't really use the bytes,
which are intended for the 8TC mode.

Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
40f05e5b Fri May 22 03:19:48 CDT 2020 Mark Starovoytov <mstarovoitov@marvell.com> net: atlantic: proper rss_ctrl1 (54c0) initialization

This patch fixes an inconsistency between code and spec, which
was found while working on the QoS implementation.

When 8TCs are used, 2 is the maximum supported number of index bits.
In a 4TC mode, we do support 3, but we shouldn't really use the bytes,
which are intended for the 8TC mode.

Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>