Searched hist:"320 eca62" (Results 1 – 3 of 3) sorted by relevance
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | irq_types.h | 320eca62 Wed Jan 20 03:22:30 CST 2021 Wayne Lin <Wayne.Lin@amd.com> drm/amd/display: Add otg vertical interrupt0 support in DCN1.0
[Why & How]
On DCN1.0, need otg vertical line interrupt to get appropriate timing
to achieve specific feature request.
Add otg vertical interrupt0 support for registers which operation is
vertical sensitive.
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/irq/dcn10/ |
| H A D | irq_service_dcn10.c | 320eca62 Wed Jan 20 03:22:30 CST 2021 Wayne Lin <Wayne.Lin@amd.com> drm/amd/display: Add otg vertical interrupt0 support in DCN1.0
[Why & How]
On DCN1.0, need otg vertical line interrupt to get appropriate timing
to achieve specific feature request.
Add otg vertical interrupt0 support for registers which operation is
vertical sensitive.
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|
| /openbmc/linux/drivers/gpu/drm/amd/display/amdgpu_dm/ |
| H A D | amdgpu_dm_irq.c | 320eca62 Wed Jan 20 03:22:30 CST 2021 Wayne Lin <Wayne.Lin@amd.com> drm/amd/display: Add otg vertical interrupt0 support in DCN1.0
[Why & How]
On DCN1.0, need otg vertical line interrupt to get appropriate timing
to achieve specific feature request.
Add otg vertical interrupt0 support for registers which operation is
vertical sensitive.
Signed-off-by: Wayne Lin <Wayne.Lin@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
|