14562236bSHarry Wentland /*
24562236bSHarry Wentland * Copyright 2015 Advanced Micro Devices, Inc.
34562236bSHarry Wentland *
44562236bSHarry Wentland * Permission is hereby granted, free of charge, to any person obtaining a
54562236bSHarry Wentland * copy of this software and associated documentation files (the "Software"),
64562236bSHarry Wentland * to deal in the Software without restriction, including without limitation
74562236bSHarry Wentland * the rights to use, copy, modify, merge, publish, distribute, sublicense,
84562236bSHarry Wentland * and/or sell copies of the Software, and to permit persons to whom the
94562236bSHarry Wentland * Software is furnished to do so, subject to the following conditions:
104562236bSHarry Wentland *
114562236bSHarry Wentland * The above copyright notice and this permission notice shall be included in
124562236bSHarry Wentland * all copies or substantial portions of the Software.
134562236bSHarry Wentland *
144562236bSHarry Wentland * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
154562236bSHarry Wentland * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
164562236bSHarry Wentland * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
174562236bSHarry Wentland * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
184562236bSHarry Wentland * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
194562236bSHarry Wentland * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
204562236bSHarry Wentland * OTHER DEALINGS IN THE SOFTWARE.
214562236bSHarry Wentland *
224562236bSHarry Wentland * Authors: AMD
234562236bSHarry Wentland *
244562236bSHarry Wentland */
254562236bSHarry Wentland
264562236bSHarry Wentland #include "dm_services_types.h"
274562236bSHarry Wentland #include "dc.h"
284562236bSHarry Wentland
294562236bSHarry Wentland #include "amdgpu.h"
304562236bSHarry Wentland #include "amdgpu_dm.h"
314562236bSHarry Wentland #include "amdgpu_dm_irq.h"
324562236bSHarry Wentland
33b8592b48SLeo Li /**
34b8592b48SLeo Li * DOC: overview
35b8592b48SLeo Li *
36b8592b48SLeo Li * DM provides another layer of IRQ management on top of what the base driver
37b8592b48SLeo Li * already provides. This is something that could be cleaned up, and is a
38b8592b48SLeo Li * future TODO item.
39b8592b48SLeo Li *
40b8592b48SLeo Li * The base driver provides IRQ source registration with DRM, handler
41b8592b48SLeo Li * registration into the base driver's IRQ table, and a handler callback
42b8592b48SLeo Li * amdgpu_irq_handler(), with which DRM calls on interrupts. This generic
43b8592b48SLeo Li * handler looks up the IRQ table, and calls the respective
44b8592b48SLeo Li * &amdgpu_irq_src_funcs.process hookups.
45b8592b48SLeo Li *
46b8592b48SLeo Li * What DM provides on top are two IRQ tables specifically for top-half and
47b8592b48SLeo Li * bottom-half IRQ handling, with the bottom-half implementing workqueues:
48b8592b48SLeo Li *
49b8592b48SLeo Li * - &amdgpu_display_manager.irq_handler_list_high_tab
50b8592b48SLeo Li * - &amdgpu_display_manager.irq_handler_list_low_tab
51b8592b48SLeo Li *
52b8592b48SLeo Li * They override the base driver's IRQ table, and the effect can be seen
53b8592b48SLeo Li * in the hooks that DM provides for &amdgpu_irq_src_funcs.process. They
54b8592b48SLeo Li * are all set to the DM generic handler amdgpu_dm_irq_handler(), which looks up
55b8592b48SLeo Li * DM's IRQ tables. However, in order for base driver to recognize this hook, DM
56b8592b48SLeo Li * still needs to register the IRQ with the base driver. See
57b8592b48SLeo Li * dce110_register_irq_handlers() and dcn10_register_irq_handlers().
58b8592b48SLeo Li *
59b8592b48SLeo Li * To expose DC's hardware interrupt toggle to the base driver, DM implements
60b8592b48SLeo Li * &amdgpu_irq_src_funcs.set hooks. Base driver calls it through
61b8592b48SLeo Li * amdgpu_irq_update() to enable or disable the interrupt.
62b8592b48SLeo Li */
63b8592b48SLeo Li
644562236bSHarry Wentland /******************************************************************************
654562236bSHarry Wentland * Private declarations.
664562236bSHarry Wentland *****************************************************************************/
674562236bSHarry Wentland
68b8592b48SLeo Li /**
69b8592b48SLeo Li * struct amdgpu_dm_irq_handler_data - Data for DM interrupt handlers.
70b8592b48SLeo Li *
71b8592b48SLeo Li * @list: Linked list entry referencing the next/previous handler
72b8592b48SLeo Li * @handler: Handler function
73b8592b48SLeo Li * @handler_arg: Argument passed to the handler when triggered
74b8592b48SLeo Li * @dm: DM which this handler belongs to
75b8592b48SLeo Li * @irq_source: DC interrupt source that this handler is registered for
76ce4f17d0SAlex Deucher * @work: work struct
77b8592b48SLeo Li */
78a7fbf17aSLeo Li struct amdgpu_dm_irq_handler_data {
794562236bSHarry Wentland struct list_head list;
804562236bSHarry Wentland interrupt_handler handler;
814562236bSHarry Wentland void *handler_arg;
824562236bSHarry Wentland
834562236bSHarry Wentland struct amdgpu_display_manager *dm;
844562236bSHarry Wentland /* DAL irq source which registered for this interrupt. */
854562236bSHarry Wentland enum dc_irq_source irq_source;
86b6f91fc1SXiaogang Chen struct work_struct work;
874562236bSHarry Wentland };
884562236bSHarry Wentland
894562236bSHarry Wentland #define DM_IRQ_TABLE_LOCK(adev, flags) \
904562236bSHarry Wentland spin_lock_irqsave(&adev->dm.irq_handler_list_table_lock, flags)
914562236bSHarry Wentland
924562236bSHarry Wentland #define DM_IRQ_TABLE_UNLOCK(adev, flags) \
934562236bSHarry Wentland spin_unlock_irqrestore(&adev->dm.irq_handler_list_table_lock, flags)
944562236bSHarry Wentland
954562236bSHarry Wentland /******************************************************************************
964562236bSHarry Wentland * Private functions.
974562236bSHarry Wentland *****************************************************************************/
984562236bSHarry Wentland
init_handler_common_data(struct amdgpu_dm_irq_handler_data * hcd,void (* ih)(void *),void * args,struct amdgpu_display_manager * dm)99a7fbf17aSLeo Li static void init_handler_common_data(struct amdgpu_dm_irq_handler_data *hcd,
1004562236bSHarry Wentland void (*ih)(void *),
1014562236bSHarry Wentland void *args,
1024562236bSHarry Wentland struct amdgpu_display_manager *dm)
1034562236bSHarry Wentland {
1044562236bSHarry Wentland hcd->handler = ih;
1054562236bSHarry Wentland hcd->handler_arg = args;
1064562236bSHarry Wentland hcd->dm = dm;
1074562236bSHarry Wentland }
1084562236bSHarry Wentland
1094562236bSHarry Wentland /**
110b8592b48SLeo Li * dm_irq_work_func() - Handle an IRQ outside of the interrupt handler proper.
1114562236bSHarry Wentland *
1124562236bSHarry Wentland * @work: work struct
1134562236bSHarry Wentland */
dm_irq_work_func(struct work_struct * work)1144562236bSHarry Wentland static void dm_irq_work_func(struct work_struct *work)
1154562236bSHarry Wentland {
116b6f91fc1SXiaogang Chen struct amdgpu_dm_irq_handler_data *handler_data =
117b6f91fc1SXiaogang Chen container_of(work, struct amdgpu_dm_irq_handler_data, work);
1184562236bSHarry Wentland
119a7fbf17aSLeo Li handler_data->handler(handler_data->handler_arg);
1204562236bSHarry Wentland
1214562236bSHarry Wentland /* Call a DAL subcomponent which registered for interrupt notification
1224562236bSHarry Wentland * at INTERRUPT_LOW_IRQ_CONTEXT.
123*2d0b69fcSSrinivasan Shanmugam * (The most common use is HPD interrupt)
124*2d0b69fcSSrinivasan Shanmugam */
1254562236bSHarry Wentland }
1264562236bSHarry Wentland
127b8592b48SLeo Li /*
128b8592b48SLeo Li * Remove a handler and return a pointer to handler list from which the
1294562236bSHarry Wentland * handler was removed.
1304562236bSHarry Wentland */
remove_irq_handler(struct amdgpu_device * adev,void * ih,const struct dc_interrupt_params * int_params)131e6375256SAlex Deucher static struct list_head *remove_irq_handler(struct amdgpu_device *adev,
1324562236bSHarry Wentland void *ih,
1334562236bSHarry Wentland const struct dc_interrupt_params *int_params)
1344562236bSHarry Wentland {
1354562236bSHarry Wentland struct list_head *hnd_list;
1364562236bSHarry Wentland struct list_head *entry, *tmp;
1374562236bSHarry Wentland struct amdgpu_dm_irq_handler_data *handler;
1384562236bSHarry Wentland unsigned long irq_table_flags;
1394562236bSHarry Wentland bool handler_removed = false;
1404562236bSHarry Wentland enum dc_irq_source irq_source;
1414562236bSHarry Wentland
1424562236bSHarry Wentland DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
1434562236bSHarry Wentland
1444562236bSHarry Wentland irq_source = int_params->irq_source;
1454562236bSHarry Wentland
1464562236bSHarry Wentland switch (int_params->int_context) {
1474562236bSHarry Wentland case INTERRUPT_HIGH_IRQ_CONTEXT:
1484562236bSHarry Wentland hnd_list = &adev->dm.irq_handler_list_high_tab[irq_source];
1494562236bSHarry Wentland break;
1504562236bSHarry Wentland case INTERRUPT_LOW_IRQ_CONTEXT:
1514562236bSHarry Wentland default:
152b6f91fc1SXiaogang Chen hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source];
1534562236bSHarry Wentland break;
1544562236bSHarry Wentland }
1554562236bSHarry Wentland
1564562236bSHarry Wentland list_for_each_safe(entry, tmp, hnd_list) {
1574562236bSHarry Wentland
1584562236bSHarry Wentland handler = list_entry(entry, struct amdgpu_dm_irq_handler_data,
159a7fbf17aSLeo Li list);
1604562236bSHarry Wentland
161ea96b12aSQingqing Zhuo if (handler == NULL)
162ea96b12aSQingqing Zhuo continue;
163ea96b12aSQingqing Zhuo
164ea96b12aSQingqing Zhuo if (ih == handler->handler) {
1654562236bSHarry Wentland /* Found our handler. Remove it from the list. */
166a7fbf17aSLeo Li list_del(&handler->list);
1674562236bSHarry Wentland handler_removed = true;
1684562236bSHarry Wentland break;
1694562236bSHarry Wentland }
1704562236bSHarry Wentland }
1714562236bSHarry Wentland
1724562236bSHarry Wentland DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
1734562236bSHarry Wentland
1744562236bSHarry Wentland if (handler_removed == false) {
1754562236bSHarry Wentland /* Not necessarily an error - caller may not
176*2d0b69fcSSrinivasan Shanmugam * know the context.
177*2d0b69fcSSrinivasan Shanmugam */
1784562236bSHarry Wentland return NULL;
1794562236bSHarry Wentland }
1804562236bSHarry Wentland
1814562236bSHarry Wentland kfree(handler);
1824562236bSHarry Wentland
1834562236bSHarry Wentland DRM_DEBUG_KMS(
1844562236bSHarry Wentland "DM_IRQ: removed irq handler: %p for: dal_src=%d, irq context=%d\n",
1854562236bSHarry Wentland ih, int_params->irq_source, int_params->int_context);
1864562236bSHarry Wentland
1874562236bSHarry Wentland return hnd_list;
1884562236bSHarry Wentland }
1894562236bSHarry Wentland
1904aa8607eSVictor Lu /**
1914aa8607eSVictor Lu * unregister_all_irq_handlers() - Cleans up handlers from the DM IRQ table
1924aa8607eSVictor Lu * @adev: The base driver device containing the DM device
1934aa8607eSVictor Lu *
1944aa8607eSVictor Lu * Go through low and high context IRQ tables and deallocate handlers.
1954aa8607eSVictor Lu */
unregister_all_irq_handlers(struct amdgpu_device * adev)1964aa8607eSVictor Lu static void unregister_all_irq_handlers(struct amdgpu_device *adev)
1974aa8607eSVictor Lu {
1984aa8607eSVictor Lu struct list_head *hnd_list_low;
1994aa8607eSVictor Lu struct list_head *hnd_list_high;
2004aa8607eSVictor Lu struct list_head *entry, *tmp;
2014aa8607eSVictor Lu struct amdgpu_dm_irq_handler_data *handler;
2024aa8607eSVictor Lu unsigned long irq_table_flags;
2034aa8607eSVictor Lu int i;
2044aa8607eSVictor Lu
2054aa8607eSVictor Lu DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
2064aa8607eSVictor Lu
2074aa8607eSVictor Lu for (i = 0; i < DAL_IRQ_SOURCES_NUMBER; i++) {
2084aa8607eSVictor Lu hnd_list_low = &adev->dm.irq_handler_list_low_tab[i];
2094aa8607eSVictor Lu hnd_list_high = &adev->dm.irq_handler_list_high_tab[i];
2104aa8607eSVictor Lu
2114aa8607eSVictor Lu list_for_each_safe(entry, tmp, hnd_list_low) {
2124aa8607eSVictor Lu
2134aa8607eSVictor Lu handler = list_entry(entry, struct amdgpu_dm_irq_handler_data,
2144aa8607eSVictor Lu list);
2154aa8607eSVictor Lu
2164aa8607eSVictor Lu if (handler == NULL || handler->handler == NULL)
2174aa8607eSVictor Lu continue;
2184aa8607eSVictor Lu
2194aa8607eSVictor Lu list_del(&handler->list);
2204aa8607eSVictor Lu kfree(handler);
2214aa8607eSVictor Lu }
2224aa8607eSVictor Lu
2234aa8607eSVictor Lu list_for_each_safe(entry, tmp, hnd_list_high) {
2244aa8607eSVictor Lu
2254aa8607eSVictor Lu handler = list_entry(entry, struct amdgpu_dm_irq_handler_data,
2264aa8607eSVictor Lu list);
2274aa8607eSVictor Lu
2284aa8607eSVictor Lu if (handler == NULL || handler->handler == NULL)
2294aa8607eSVictor Lu continue;
2304aa8607eSVictor Lu
2314aa8607eSVictor Lu list_del(&handler->list);
2324aa8607eSVictor Lu kfree(handler);
2334aa8607eSVictor Lu }
2344aa8607eSVictor Lu }
2354aa8607eSVictor Lu
2364aa8607eSVictor Lu DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
2374aa8607eSVictor Lu }
2384aa8607eSVictor Lu
239e6375256SAlex Deucher static bool
validate_irq_registration_params(struct dc_interrupt_params * int_params,void (* ih)(void *))240e6375256SAlex Deucher validate_irq_registration_params(struct dc_interrupt_params *int_params,
2414562236bSHarry Wentland void (*ih)(void *))
2424562236bSHarry Wentland {
2434562236bSHarry Wentland if (NULL == int_params || NULL == ih) {
2444562236bSHarry Wentland DRM_ERROR("DM_IRQ: invalid input!\n");
2454562236bSHarry Wentland return false;
2464562236bSHarry Wentland }
2474562236bSHarry Wentland
2484562236bSHarry Wentland if (int_params->int_context >= INTERRUPT_CONTEXT_NUMBER) {
2494562236bSHarry Wentland DRM_ERROR("DM_IRQ: invalid context: %d!\n",
2504562236bSHarry Wentland int_params->int_context);
2514562236bSHarry Wentland return false;
2524562236bSHarry Wentland }
2534562236bSHarry Wentland
2544562236bSHarry Wentland if (!DAL_VALID_IRQ_SRC_NUM(int_params->irq_source)) {
2554562236bSHarry Wentland DRM_ERROR("DM_IRQ: invalid irq_source: %d!\n",
2564562236bSHarry Wentland int_params->irq_source);
2574562236bSHarry Wentland return false;
2584562236bSHarry Wentland }
2594562236bSHarry Wentland
2604562236bSHarry Wentland return true;
2614562236bSHarry Wentland }
2624562236bSHarry Wentland
validate_irq_unregistration_params(enum dc_irq_source irq_source,irq_handler_idx handler_idx)263e6375256SAlex Deucher static bool validate_irq_unregistration_params(enum dc_irq_source irq_source,
2644562236bSHarry Wentland irq_handler_idx handler_idx)
2654562236bSHarry Wentland {
266*2d0b69fcSSrinivasan Shanmugam if (handler_idx == DAL_INVALID_IRQ_HANDLER_IDX) {
2674562236bSHarry Wentland DRM_ERROR("DM_IRQ: invalid handler_idx==NULL!\n");
2684562236bSHarry Wentland return false;
2694562236bSHarry Wentland }
2704562236bSHarry Wentland
2714562236bSHarry Wentland if (!DAL_VALID_IRQ_SRC_NUM(irq_source)) {
2724562236bSHarry Wentland DRM_ERROR("DM_IRQ: invalid irq_source:%d!\n", irq_source);
2734562236bSHarry Wentland return false;
2744562236bSHarry Wentland }
2754562236bSHarry Wentland
2764562236bSHarry Wentland return true;
2774562236bSHarry Wentland }
2784562236bSHarry Wentland /******************************************************************************
2794562236bSHarry Wentland * Public functions.
2804562236bSHarry Wentland *
2814562236bSHarry Wentland * Note: caller is responsible for input validation.
2824562236bSHarry Wentland *****************************************************************************/
2834562236bSHarry Wentland
284b8592b48SLeo Li /**
285b8592b48SLeo Li * amdgpu_dm_irq_register_interrupt() - Register a handler within DM.
286b8592b48SLeo Li * @adev: The base driver device containing the DM device.
287b8592b48SLeo Li * @int_params: Interrupt parameters containing the source, and handler context
288b8592b48SLeo Li * @ih: Function pointer to the interrupt handler to register
289b8592b48SLeo Li * @handler_args: Arguments passed to the handler when the interrupt occurs
290b8592b48SLeo Li *
291b8592b48SLeo Li * Register an interrupt handler for the given IRQ source, under the given
292b8592b48SLeo Li * context. The context can either be high or low. High context handlers are
293b8592b48SLeo Li * executed directly within ISR context, while low context is executed within a
294b8592b48SLeo Li * workqueue, thereby allowing operations that sleep.
295b8592b48SLeo Li *
296b8592b48SLeo Li * Registered handlers are called in a FIFO manner, i.e. the most recently
297b8592b48SLeo Li * registered handler will be called first.
298b8592b48SLeo Li *
299b8592b48SLeo Li * Return: Handler data &struct amdgpu_dm_irq_handler_data containing the IRQ
300b8592b48SLeo Li * source, handler function, and args
301b8592b48SLeo Li */
amdgpu_dm_irq_register_interrupt(struct amdgpu_device * adev,struct dc_interrupt_params * int_params,void (* ih)(void *),void * handler_args)302e6375256SAlex Deucher void *amdgpu_dm_irq_register_interrupt(struct amdgpu_device *adev,
3034562236bSHarry Wentland struct dc_interrupt_params *int_params,
3044562236bSHarry Wentland void (*ih)(void *),
3054562236bSHarry Wentland void *handler_args)
3064562236bSHarry Wentland {
3074562236bSHarry Wentland struct list_head *hnd_list;
3084562236bSHarry Wentland struct amdgpu_dm_irq_handler_data *handler_data;
3094562236bSHarry Wentland unsigned long irq_table_flags;
3104562236bSHarry Wentland enum dc_irq_source irq_source;
3114562236bSHarry Wentland
3124562236bSHarry Wentland if (false == validate_irq_registration_params(int_params, ih))
3134562236bSHarry Wentland return DAL_INVALID_IRQ_HANDLER_IDX;
3144562236bSHarry Wentland
3154562236bSHarry Wentland handler_data = kzalloc(sizeof(*handler_data), GFP_KERNEL);
3164562236bSHarry Wentland if (!handler_data) {
3174562236bSHarry Wentland DRM_ERROR("DM_IRQ: failed to allocate irq handler!\n");
3184562236bSHarry Wentland return DAL_INVALID_IRQ_HANDLER_IDX;
3194562236bSHarry Wentland }
3204562236bSHarry Wentland
321a7fbf17aSLeo Li init_handler_common_data(handler_data, ih, handler_args, &adev->dm);
3224562236bSHarry Wentland
3234562236bSHarry Wentland irq_source = int_params->irq_source;
3244562236bSHarry Wentland
3254562236bSHarry Wentland handler_data->irq_source = irq_source;
3264562236bSHarry Wentland
3274562236bSHarry Wentland /* Lock the list, add the handler. */
3284562236bSHarry Wentland DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
3294562236bSHarry Wentland
3304562236bSHarry Wentland switch (int_params->int_context) {
3314562236bSHarry Wentland case INTERRUPT_HIGH_IRQ_CONTEXT:
3324562236bSHarry Wentland hnd_list = &adev->dm.irq_handler_list_high_tab[irq_source];
3334562236bSHarry Wentland break;
3344562236bSHarry Wentland case INTERRUPT_LOW_IRQ_CONTEXT:
3354562236bSHarry Wentland default:
336b6f91fc1SXiaogang Chen hnd_list = &adev->dm.irq_handler_list_low_tab[irq_source];
337b6f91fc1SXiaogang Chen INIT_WORK(&handler_data->work, dm_irq_work_func);
3384562236bSHarry Wentland break;
3394562236bSHarry Wentland }
3404562236bSHarry Wentland
341a7fbf17aSLeo Li list_add_tail(&handler_data->list, hnd_list);
3424562236bSHarry Wentland
3434562236bSHarry Wentland DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
3444562236bSHarry Wentland
3454562236bSHarry Wentland /* This pointer will be stored by code which requested interrupt
3464562236bSHarry Wentland * registration.
3474562236bSHarry Wentland * The same pointer will be needed in order to unregister the
348*2d0b69fcSSrinivasan Shanmugam * interrupt.
349*2d0b69fcSSrinivasan Shanmugam */
3504562236bSHarry Wentland
3514562236bSHarry Wentland DRM_DEBUG_KMS(
3524562236bSHarry Wentland "DM_IRQ: added irq handler: %p for: dal_src=%d, irq context=%d\n",
3534562236bSHarry Wentland handler_data,
3544562236bSHarry Wentland irq_source,
3554562236bSHarry Wentland int_params->int_context);
3564562236bSHarry Wentland
3574562236bSHarry Wentland return handler_data;
3584562236bSHarry Wentland }
3594562236bSHarry Wentland
360b8592b48SLeo Li /**
361b8592b48SLeo Li * amdgpu_dm_irq_unregister_interrupt() - Remove a handler from the DM IRQ table
362b8592b48SLeo Li * @adev: The base driver device containing the DM device
363b8592b48SLeo Li * @irq_source: IRQ source to remove the given handler from
364b8592b48SLeo Li * @ih: Function pointer to the interrupt handler to unregister
365b8592b48SLeo Li *
366b8592b48SLeo Li * Go through both low and high context IRQ tables, and find the given handler
367b8592b48SLeo Li * for the given irq source. If found, remove it. Otherwise, do nothing.
368b8592b48SLeo Li */
amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device * adev,enum dc_irq_source irq_source,void * ih)369e6375256SAlex Deucher void amdgpu_dm_irq_unregister_interrupt(struct amdgpu_device *adev,
3704562236bSHarry Wentland enum dc_irq_source irq_source,
3714562236bSHarry Wentland void *ih)
3724562236bSHarry Wentland {
3734562236bSHarry Wentland struct list_head *handler_list;
3744562236bSHarry Wentland struct dc_interrupt_params int_params;
3754562236bSHarry Wentland int i;
3764562236bSHarry Wentland
3774562236bSHarry Wentland if (false == validate_irq_unregistration_params(irq_source, ih))
3784562236bSHarry Wentland return;
3794562236bSHarry Wentland
3804562236bSHarry Wentland memset(&int_params, 0, sizeof(int_params));
3814562236bSHarry Wentland
3824562236bSHarry Wentland int_params.irq_source = irq_source;
3834562236bSHarry Wentland
3844562236bSHarry Wentland for (i = 0; i < INTERRUPT_CONTEXT_NUMBER; i++) {
3854562236bSHarry Wentland
3864562236bSHarry Wentland int_params.int_context = i;
3874562236bSHarry Wentland
3884562236bSHarry Wentland handler_list = remove_irq_handler(adev, ih, &int_params);
3894562236bSHarry Wentland
3904562236bSHarry Wentland if (handler_list != NULL)
3914562236bSHarry Wentland break;
3924562236bSHarry Wentland }
3934562236bSHarry Wentland
3944562236bSHarry Wentland if (handler_list == NULL) {
3954562236bSHarry Wentland /* If we got here, it means we searched all irq contexts
396*2d0b69fcSSrinivasan Shanmugam * for this irq source, but the handler was not found.
397*2d0b69fcSSrinivasan Shanmugam */
3984562236bSHarry Wentland DRM_ERROR(
3994562236bSHarry Wentland "DM_IRQ: failed to find irq handler:%p for irq_source:%d!\n",
4004562236bSHarry Wentland ih, irq_source);
4014562236bSHarry Wentland }
4024562236bSHarry Wentland }
4034562236bSHarry Wentland
404b8592b48SLeo Li /**
405b8592b48SLeo Li * amdgpu_dm_irq_init() - Initialize DM IRQ management
406b8592b48SLeo Li * @adev: The base driver device containing the DM device
407b8592b48SLeo Li *
408b8592b48SLeo Li * Initialize DM's high and low context IRQ tables.
409b8592b48SLeo Li *
410b8592b48SLeo Li * The N by M table contains N IRQ sources, with M
411b8592b48SLeo Li * &struct amdgpu_dm_irq_handler_data hooked together in a linked list. The
412b8592b48SLeo Li * list_heads are initialized here. When an interrupt n is triggered, all m
413b8592b48SLeo Li * handlers are called in sequence, FIFO according to registration order.
414b8592b48SLeo Li *
415b8592b48SLeo Li * The low context table requires special steps to initialize, since handlers
416b8592b48SLeo Li * will be deferred to a workqueue. See &struct irq_list_head.
417b8592b48SLeo Li */
amdgpu_dm_irq_init(struct amdgpu_device * adev)418e6375256SAlex Deucher int amdgpu_dm_irq_init(struct amdgpu_device *adev)
4194562236bSHarry Wentland {
4204562236bSHarry Wentland int src;
421b6f91fc1SXiaogang Chen struct list_head *lh;
4224562236bSHarry Wentland
4234562236bSHarry Wentland DRM_DEBUG_KMS("DM_IRQ\n");
4244562236bSHarry Wentland
4254562236bSHarry Wentland spin_lock_init(&adev->dm.irq_handler_list_table_lock);
4264562236bSHarry Wentland
4274562236bSHarry Wentland for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) {
4284562236bSHarry Wentland /* low context handler list init */
4294562236bSHarry Wentland lh = &adev->dm.irq_handler_list_low_tab[src];
430b6f91fc1SXiaogang Chen INIT_LIST_HEAD(lh);
4314562236bSHarry Wentland /* high context handler init */
4324562236bSHarry Wentland INIT_LIST_HEAD(&adev->dm.irq_handler_list_high_tab[src]);
4334562236bSHarry Wentland }
4344562236bSHarry Wentland
4354562236bSHarry Wentland return 0;
4364562236bSHarry Wentland }
4374562236bSHarry Wentland
438b8592b48SLeo Li /**
439b8592b48SLeo Li * amdgpu_dm_irq_fini() - Tear down DM IRQ management
440b8592b48SLeo Li * @adev: The base driver device containing the DM device
441b8592b48SLeo Li *
442b8592b48SLeo Li * Flush all work within the low context IRQ table.
443b8592b48SLeo Li */
amdgpu_dm_irq_fini(struct amdgpu_device * adev)444e6375256SAlex Deucher void amdgpu_dm_irq_fini(struct amdgpu_device *adev)
4454562236bSHarry Wentland {
4464562236bSHarry Wentland int src;
447b6f91fc1SXiaogang Chen struct list_head *lh;
448b6f91fc1SXiaogang Chen struct list_head *entry, *tmp;
449b6f91fc1SXiaogang Chen struct amdgpu_dm_irq_handler_data *handler;
450ad64dc01SMikita Lipski unsigned long irq_table_flags;
451b6f91fc1SXiaogang Chen
4524562236bSHarry Wentland DRM_DEBUG_KMS("DM_IRQ: releasing resources.\n");
4534562236bSHarry Wentland for (src = 0; src < DAL_IRQ_SOURCES_NUMBER; src++) {
454ad64dc01SMikita Lipski DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
4554562236bSHarry Wentland /* The handler was removed from the table,
4564562236bSHarry Wentland * it means it is safe to flush all the 'work'
457*2d0b69fcSSrinivasan Shanmugam * (because no code can schedule a new one).
458*2d0b69fcSSrinivasan Shanmugam */
4594562236bSHarry Wentland lh = &adev->dm.irq_handler_list_low_tab[src];
460ad64dc01SMikita Lipski DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
461b6f91fc1SXiaogang Chen
462b6f91fc1SXiaogang Chen if (!list_empty(lh)) {
463b6f91fc1SXiaogang Chen list_for_each_safe(entry, tmp, lh) {
464b6f91fc1SXiaogang Chen handler = list_entry(
465b6f91fc1SXiaogang Chen entry,
466b6f91fc1SXiaogang Chen struct amdgpu_dm_irq_handler_data,
467b6f91fc1SXiaogang Chen list);
468b6f91fc1SXiaogang Chen flush_work(&handler->work);
469b6f91fc1SXiaogang Chen }
470b6f91fc1SXiaogang Chen }
4714562236bSHarry Wentland }
4724aa8607eSVictor Lu /* Deallocate handlers from the table. */
4734aa8607eSVictor Lu unregister_all_irq_handlers(adev);
4744562236bSHarry Wentland }
4754562236bSHarry Wentland
amdgpu_dm_irq_suspend(struct amdgpu_device * adev)476e6375256SAlex Deucher int amdgpu_dm_irq_suspend(struct amdgpu_device *adev)
4774562236bSHarry Wentland {
4784562236bSHarry Wentland int src;
4794562236bSHarry Wentland struct list_head *hnd_list_h;
4804562236bSHarry Wentland struct list_head *hnd_list_l;
4814562236bSHarry Wentland unsigned long irq_table_flags;
482b6f91fc1SXiaogang Chen struct list_head *entry, *tmp;
483b6f91fc1SXiaogang Chen struct amdgpu_dm_irq_handler_data *handler;
4844562236bSHarry Wentland
4854562236bSHarry Wentland DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
4864562236bSHarry Wentland
4874562236bSHarry Wentland DRM_DEBUG_KMS("DM_IRQ: suspend\n");
4884562236bSHarry Wentland
4899faa4237SAndrey Grodzovsky /**
4909faa4237SAndrey Grodzovsky * Disable HW interrupt for HPD and HPDRX only since FLIP and VBLANK
4919faa4237SAndrey Grodzovsky * will be disabled from manage_dm_interrupts on disable CRTC.
4929faa4237SAndrey Grodzovsky */
493c018b04bSRoman Li for (src = DC_IRQ_SOURCE_HPD1; src <= DC_IRQ_SOURCE_HPD6RX; src++) {
494b6f91fc1SXiaogang Chen hnd_list_l = &adev->dm.irq_handler_list_low_tab[src];
4954562236bSHarry Wentland hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
4964562236bSHarry Wentland if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
4974562236bSHarry Wentland dc_interrupt_set(adev->dm.dc, src, false);
4984562236bSHarry Wentland
4994562236bSHarry Wentland DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
5004562236bSHarry Wentland
501b6f91fc1SXiaogang Chen if (!list_empty(hnd_list_l)) {
502b6f91fc1SXiaogang Chen list_for_each_safe(entry, tmp, hnd_list_l) {
503b6f91fc1SXiaogang Chen handler = list_entry(
504b6f91fc1SXiaogang Chen entry,
505b6f91fc1SXiaogang Chen struct amdgpu_dm_irq_handler_data,
506b6f91fc1SXiaogang Chen list);
507b6f91fc1SXiaogang Chen flush_work(&handler->work);
508b6f91fc1SXiaogang Chen }
509b6f91fc1SXiaogang Chen }
5104562236bSHarry Wentland DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
5114562236bSHarry Wentland }
5124562236bSHarry Wentland
5134562236bSHarry Wentland DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
5144562236bSHarry Wentland return 0;
5154562236bSHarry Wentland }
5164562236bSHarry Wentland
amdgpu_dm_irq_resume_early(struct amdgpu_device * adev)5174562236bSHarry Wentland int amdgpu_dm_irq_resume_early(struct amdgpu_device *adev)
5184562236bSHarry Wentland {
5194562236bSHarry Wentland int src;
5204562236bSHarry Wentland struct list_head *hnd_list_h, *hnd_list_l;
5214562236bSHarry Wentland unsigned long irq_table_flags;
5224562236bSHarry Wentland
5234562236bSHarry Wentland DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
5244562236bSHarry Wentland
5254562236bSHarry Wentland DRM_DEBUG_KMS("DM_IRQ: early resume\n");
5264562236bSHarry Wentland
5274562236bSHarry Wentland /* re-enable short pulse interrupts HW interrupt */
528c018b04bSRoman Li for (src = DC_IRQ_SOURCE_HPD1RX; src <= DC_IRQ_SOURCE_HPD6RX; src++) {
529b6f91fc1SXiaogang Chen hnd_list_l = &adev->dm.irq_handler_list_low_tab[src];
5304562236bSHarry Wentland hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
5314562236bSHarry Wentland if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
5324562236bSHarry Wentland dc_interrupt_set(adev->dm.dc, src, true);
5334562236bSHarry Wentland }
5344562236bSHarry Wentland
5354562236bSHarry Wentland DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
5364562236bSHarry Wentland
5374562236bSHarry Wentland return 0;
5384562236bSHarry Wentland }
5394562236bSHarry Wentland
amdgpu_dm_irq_resume_late(struct amdgpu_device * adev)5409faa4237SAndrey Grodzovsky int amdgpu_dm_irq_resume_late(struct amdgpu_device *adev)
5414562236bSHarry Wentland {
5424562236bSHarry Wentland int src;
5434562236bSHarry Wentland struct list_head *hnd_list_h, *hnd_list_l;
5444562236bSHarry Wentland unsigned long irq_table_flags;
5454562236bSHarry Wentland
5464562236bSHarry Wentland DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
5474562236bSHarry Wentland
5484562236bSHarry Wentland DRM_DEBUG_KMS("DM_IRQ: resume\n");
5494562236bSHarry Wentland
5509faa4237SAndrey Grodzovsky /**
5519faa4237SAndrey Grodzovsky * Renable HW interrupt for HPD and only since FLIP and VBLANK
5529faa4237SAndrey Grodzovsky * will be enabled from manage_dm_interrupts on enable CRTC.
5539faa4237SAndrey Grodzovsky */
55496687275SRoman Li for (src = DC_IRQ_SOURCE_HPD1; src <= DC_IRQ_SOURCE_HPD6; src++) {
555b6f91fc1SXiaogang Chen hnd_list_l = &adev->dm.irq_handler_list_low_tab[src];
5564562236bSHarry Wentland hnd_list_h = &adev->dm.irq_handler_list_high_tab[src];
5574562236bSHarry Wentland if (!list_empty(hnd_list_l) || !list_empty(hnd_list_h))
5584562236bSHarry Wentland dc_interrupt_set(adev->dm.dc, src, true);
5594562236bSHarry Wentland }
5604562236bSHarry Wentland
5614562236bSHarry Wentland DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
5624562236bSHarry Wentland return 0;
5634562236bSHarry Wentland }
5644562236bSHarry Wentland
565b8592b48SLeo Li /*
5664562236bSHarry Wentland * amdgpu_dm_irq_schedule_work - schedule all work items registered for the
5674562236bSHarry Wentland * "irq_source".
5684562236bSHarry Wentland */
amdgpu_dm_irq_schedule_work(struct amdgpu_device * adev,enum dc_irq_source irq_source)569e6375256SAlex Deucher static void amdgpu_dm_irq_schedule_work(struct amdgpu_device *adev,
5704562236bSHarry Wentland enum dc_irq_source irq_source)
5714562236bSHarry Wentland {
572b6f91fc1SXiaogang Chen struct list_head *handler_list = &adev->dm.irq_handler_list_low_tab[irq_source];
573b6f91fc1SXiaogang Chen struct amdgpu_dm_irq_handler_data *handler_data;
574b6f91fc1SXiaogang Chen bool work_queued = false;
5754562236bSHarry Wentland
576b6f91fc1SXiaogang Chen if (list_empty(handler_list))
577b6f91fc1SXiaogang Chen return;
5784562236bSHarry Wentland
579b6f91fc1SXiaogang Chen list_for_each_entry(handler_data, handler_list, list) {
58008f3dddbSColin Ian King if (queue_work(system_highpri_wq, &handler_data->work)) {
581b6f91fc1SXiaogang Chen work_queued = true;
582b6f91fc1SXiaogang Chen break;
583b6f91fc1SXiaogang Chen }
5844562236bSHarry Wentland }
5854562236bSHarry Wentland
586b6f91fc1SXiaogang Chen if (!work_queued) {
587b6f91fc1SXiaogang Chen struct amdgpu_dm_irq_handler_data *handler_data_add;
588b6f91fc1SXiaogang Chen /*get the amdgpu_dm_irq_handler_data of first item pointed by handler_list*/
589b6f91fc1SXiaogang Chen handler_data = container_of(handler_list->next, struct amdgpu_dm_irq_handler_data, list);
590b6f91fc1SXiaogang Chen
591b6f91fc1SXiaogang Chen /*allocate a new amdgpu_dm_irq_handler_data*/
5920cde63a8SAnson Jacob handler_data_add = kzalloc(sizeof(*handler_data), GFP_ATOMIC);
593b6f91fc1SXiaogang Chen if (!handler_data_add) {
594b6f91fc1SXiaogang Chen DRM_ERROR("DM_IRQ: failed to allocate irq handler!\n");
595b6f91fc1SXiaogang Chen return;
596b6f91fc1SXiaogang Chen }
597b6f91fc1SXiaogang Chen
598b6f91fc1SXiaogang Chen /*copy new amdgpu_dm_irq_handler_data members from handler_data*/
599b6f91fc1SXiaogang Chen handler_data_add->handler = handler_data->handler;
600b6f91fc1SXiaogang Chen handler_data_add->handler_arg = handler_data->handler_arg;
601b6f91fc1SXiaogang Chen handler_data_add->dm = handler_data->dm;
602b6f91fc1SXiaogang Chen handler_data_add->irq_source = irq_source;
603b6f91fc1SXiaogang Chen
604b6f91fc1SXiaogang Chen list_add_tail(&handler_data_add->list, handler_list);
605b6f91fc1SXiaogang Chen
606b6f91fc1SXiaogang Chen INIT_WORK(&handler_data_add->work, dm_irq_work_func);
607b6f91fc1SXiaogang Chen
608b6f91fc1SXiaogang Chen if (queue_work(system_highpri_wq, &handler_data_add->work))
609b6f91fc1SXiaogang Chen DRM_DEBUG("Queued work for handling interrupt from "
610b6f91fc1SXiaogang Chen "display for IRQ source %d\n",
611b6f91fc1SXiaogang Chen irq_source);
612b6f91fc1SXiaogang Chen else
613b6f91fc1SXiaogang Chen DRM_ERROR("Failed to queue work for handling interrupt "
614b6f91fc1SXiaogang Chen "from display for IRQ source %d\n",
615b6f91fc1SXiaogang Chen irq_source);
616b6f91fc1SXiaogang Chen }
6174562236bSHarry Wentland }
6184562236bSHarry Wentland
619b8592b48SLeo Li /*
620b8592b48SLeo Li * amdgpu_dm_irq_immediate_work
6214562236bSHarry Wentland * Callback high irq work immediately, don't send to work queue
6224562236bSHarry Wentland */
amdgpu_dm_irq_immediate_work(struct amdgpu_device * adev,enum dc_irq_source irq_source)623e6375256SAlex Deucher static void amdgpu_dm_irq_immediate_work(struct amdgpu_device *adev,
6244562236bSHarry Wentland enum dc_irq_source irq_source)
6254562236bSHarry Wentland {
6264562236bSHarry Wentland struct amdgpu_dm_irq_handler_data *handler_data;
6274562236bSHarry Wentland unsigned long irq_table_flags;
6284562236bSHarry Wentland
6294562236bSHarry Wentland DM_IRQ_TABLE_LOCK(adev, irq_table_flags);
6304562236bSHarry Wentland
631b0d7ecd7SWambui Karuga list_for_each_entry(handler_data,
632b0d7ecd7SWambui Karuga &adev->dm.irq_handler_list_high_tab[irq_source],
633b0d7ecd7SWambui Karuga list) {
6344562236bSHarry Wentland /* Call a subcomponent which registered for immediate
635*2d0b69fcSSrinivasan Shanmugam * interrupt notification
636*2d0b69fcSSrinivasan Shanmugam */
637a7fbf17aSLeo Li handler_data->handler(handler_data->handler_arg);
6384562236bSHarry Wentland }
6394562236bSHarry Wentland
6404562236bSHarry Wentland DM_IRQ_TABLE_UNLOCK(adev, irq_table_flags);
6414562236bSHarry Wentland }
6424562236bSHarry Wentland
643b8592b48SLeo Li /**
644b8592b48SLeo Li * amdgpu_dm_irq_handler - Generic DM IRQ handler
645b8592b48SLeo Li * @adev: amdgpu base driver device containing the DM device
646b8592b48SLeo Li * @source: Unused
647b8592b48SLeo Li * @entry: Data about the triggered interrupt
6484562236bSHarry Wentland *
649b8592b48SLeo Li * Calls all registered high irq work immediately, and schedules work for low
650b8592b48SLeo Li * irq. The DM IRQ table is used to find the corresponding handlers.
6514562236bSHarry Wentland */
amdgpu_dm_irq_handler(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)6528db02ca3SAlex Deucher static int amdgpu_dm_irq_handler(struct amdgpu_device *adev,
6534562236bSHarry Wentland struct amdgpu_irq_src *source,
6544562236bSHarry Wentland struct amdgpu_iv_entry *entry)
6554562236bSHarry Wentland {
6564562236bSHarry Wentland
6574562236bSHarry Wentland enum dc_irq_source src =
6584562236bSHarry Wentland dc_interrupt_to_irq_source(
6594562236bSHarry Wentland adev->dm.dc,
6604562236bSHarry Wentland entry->src_id,
6614562236bSHarry Wentland entry->src_data[0]);
6624562236bSHarry Wentland
6634562236bSHarry Wentland dc_interrupt_ack(adev->dm.dc, src);
6644562236bSHarry Wentland
6654562236bSHarry Wentland /* Call high irq work immediately */
6664562236bSHarry Wentland amdgpu_dm_irq_immediate_work(adev, src);
6674562236bSHarry Wentland /*Schedule low_irq work */
6684562236bSHarry Wentland amdgpu_dm_irq_schedule_work(adev, src);
6694562236bSHarry Wentland
6704562236bSHarry Wentland return 0;
6714562236bSHarry Wentland }
6724562236bSHarry Wentland
amdgpu_dm_hpd_to_dal_irq_source(unsigned int type)673*2d0b69fcSSrinivasan Shanmugam static enum dc_irq_source amdgpu_dm_hpd_to_dal_irq_source(unsigned int type)
6744562236bSHarry Wentland {
6754562236bSHarry Wentland switch (type) {
6764562236bSHarry Wentland case AMDGPU_HPD_1:
6774562236bSHarry Wentland return DC_IRQ_SOURCE_HPD1;
6784562236bSHarry Wentland case AMDGPU_HPD_2:
6794562236bSHarry Wentland return DC_IRQ_SOURCE_HPD2;
6804562236bSHarry Wentland case AMDGPU_HPD_3:
6814562236bSHarry Wentland return DC_IRQ_SOURCE_HPD3;
6824562236bSHarry Wentland case AMDGPU_HPD_4:
6834562236bSHarry Wentland return DC_IRQ_SOURCE_HPD4;
6844562236bSHarry Wentland case AMDGPU_HPD_5:
6854562236bSHarry Wentland return DC_IRQ_SOURCE_HPD5;
6864562236bSHarry Wentland case AMDGPU_HPD_6:
6874562236bSHarry Wentland return DC_IRQ_SOURCE_HPD6;
6884562236bSHarry Wentland default:
6894562236bSHarry Wentland return DC_IRQ_SOURCE_INVALID;
6904562236bSHarry Wentland }
6914562236bSHarry Wentland }
6924562236bSHarry Wentland
amdgpu_dm_set_hpd_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)6934562236bSHarry Wentland static int amdgpu_dm_set_hpd_irq_state(struct amdgpu_device *adev,
6944562236bSHarry Wentland struct amdgpu_irq_src *source,
695*2d0b69fcSSrinivasan Shanmugam unsigned int type,
6964562236bSHarry Wentland enum amdgpu_interrupt_state state)
6974562236bSHarry Wentland {
6984562236bSHarry Wentland enum dc_irq_source src = amdgpu_dm_hpd_to_dal_irq_source(type);
6994562236bSHarry Wentland bool st = (state == AMDGPU_IRQ_STATE_ENABLE);
7004562236bSHarry Wentland
7014562236bSHarry Wentland dc_interrupt_set(adev->dm.dc, src, st);
7024562236bSHarry Wentland return 0;
7034562236bSHarry Wentland }
7044562236bSHarry Wentland
dm_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int crtc_id,enum amdgpu_interrupt_state state,const enum irq_type dal_irq_type,const char * func)705e6375256SAlex Deucher static inline int dm_irq_state(struct amdgpu_device *adev,
7064562236bSHarry Wentland struct amdgpu_irq_src *source,
707*2d0b69fcSSrinivasan Shanmugam unsigned int crtc_id,
7084562236bSHarry Wentland enum amdgpu_interrupt_state state,
7094562236bSHarry Wentland const enum irq_type dal_irq_type,
7104562236bSHarry Wentland const char *func)
7114562236bSHarry Wentland {
7124562236bSHarry Wentland bool st;
7134562236bSHarry Wentland enum dc_irq_source irq_source;
7144562236bSHarry Wentland
7154562236bSHarry Wentland struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc_id];
7164562236bSHarry Wentland
7174562236bSHarry Wentland if (!acrtc) {
7184562236bSHarry Wentland DRM_ERROR(
7194562236bSHarry Wentland "%s: crtc is NULL at id :%d\n",
7204562236bSHarry Wentland func,
7214562236bSHarry Wentland crtc_id);
7224562236bSHarry Wentland return 0;
7234562236bSHarry Wentland }
7244562236bSHarry Wentland
7254ea7fc09SMikita Lipski if (acrtc->otg_inst == -1)
7264ea7fc09SMikita Lipski return 0;
7274ea7fc09SMikita Lipski
7284562236bSHarry Wentland irq_source = dal_irq_type + acrtc->otg_inst;
7294562236bSHarry Wentland
7304562236bSHarry Wentland st = (state == AMDGPU_IRQ_STATE_ENABLE);
7314562236bSHarry Wentland
7324562236bSHarry Wentland dc_interrupt_set(adev->dm.dc, irq_source, st);
7334562236bSHarry Wentland return 0;
7344562236bSHarry Wentland }
7354562236bSHarry Wentland
amdgpu_dm_set_pflip_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int crtc_id,enum amdgpu_interrupt_state state)7364562236bSHarry Wentland static int amdgpu_dm_set_pflip_irq_state(struct amdgpu_device *adev,
7374562236bSHarry Wentland struct amdgpu_irq_src *source,
738*2d0b69fcSSrinivasan Shanmugam unsigned int crtc_id,
7394562236bSHarry Wentland enum amdgpu_interrupt_state state)
7404562236bSHarry Wentland {
7414562236bSHarry Wentland return dm_irq_state(
7424562236bSHarry Wentland adev,
7434562236bSHarry Wentland source,
7444562236bSHarry Wentland crtc_id,
7454562236bSHarry Wentland state,
7464562236bSHarry Wentland IRQ_TYPE_PFLIP,
7474562236bSHarry Wentland __func__);
7484562236bSHarry Wentland }
7494562236bSHarry Wentland
amdgpu_dm_set_crtc_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int crtc_id,enum amdgpu_interrupt_state state)7504562236bSHarry Wentland static int amdgpu_dm_set_crtc_irq_state(struct amdgpu_device *adev,
7514562236bSHarry Wentland struct amdgpu_irq_src *source,
752*2d0b69fcSSrinivasan Shanmugam unsigned int crtc_id,
7534562236bSHarry Wentland enum amdgpu_interrupt_state state)
7544562236bSHarry Wentland {
7554562236bSHarry Wentland return dm_irq_state(
7564562236bSHarry Wentland adev,
7574562236bSHarry Wentland source,
7584562236bSHarry Wentland crtc_id,
7594562236bSHarry Wentland state,
760b57de80aSAndrey Grodzovsky IRQ_TYPE_VBLANK,
7614562236bSHarry Wentland __func__);
7624562236bSHarry Wentland }
7634562236bSHarry Wentland
amdgpu_dm_set_vline0_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int crtc_id,enum amdgpu_interrupt_state state)764320eca62SWayne Lin static int amdgpu_dm_set_vline0_irq_state(struct amdgpu_device *adev,
765320eca62SWayne Lin struct amdgpu_irq_src *source,
766320eca62SWayne Lin unsigned int crtc_id,
767320eca62SWayne Lin enum amdgpu_interrupt_state state)
768320eca62SWayne Lin {
769320eca62SWayne Lin return dm_irq_state(
770320eca62SWayne Lin adev,
771320eca62SWayne Lin source,
772320eca62SWayne Lin crtc_id,
773320eca62SWayne Lin state,
774320eca62SWayne Lin IRQ_TYPE_VLINE0,
775320eca62SWayne Lin __func__);
776320eca62SWayne Lin }
777320eca62SWayne Lin
amdgpu_dm_set_dmub_outbox_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int crtc_id,enum amdgpu_interrupt_state state)77881927e28SJude Shih static int amdgpu_dm_set_dmub_outbox_irq_state(struct amdgpu_device *adev,
77981927e28SJude Shih struct amdgpu_irq_src *source,
78081927e28SJude Shih unsigned int crtc_id,
78181927e28SJude Shih enum amdgpu_interrupt_state state)
78281927e28SJude Shih {
78381927e28SJude Shih enum dc_irq_source irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX;
78481927e28SJude Shih bool st = (state == AMDGPU_IRQ_STATE_ENABLE);
78581927e28SJude Shih
78681927e28SJude Shih dc_interrupt_set(adev->dm.dc, irq_source, st);
78781927e28SJude Shih return 0;
78881927e28SJude Shih }
78981927e28SJude Shih
amdgpu_dm_set_vupdate_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int crtc_id,enum amdgpu_interrupt_state state)790d2574c33SMario Kleiner static int amdgpu_dm_set_vupdate_irq_state(struct amdgpu_device *adev,
791d2574c33SMario Kleiner struct amdgpu_irq_src *source,
792d2574c33SMario Kleiner unsigned int crtc_id,
793d2574c33SMario Kleiner enum amdgpu_interrupt_state state)
794d2574c33SMario Kleiner {
795d2574c33SMario Kleiner return dm_irq_state(
796d2574c33SMario Kleiner adev,
797d2574c33SMario Kleiner source,
798d2574c33SMario Kleiner crtc_id,
799d2574c33SMario Kleiner state,
800d2574c33SMario Kleiner IRQ_TYPE_VUPDATE,
801d2574c33SMario Kleiner __func__);
802d2574c33SMario Kleiner }
803d2574c33SMario Kleiner
amdgpu_dm_set_dmub_trace_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned int type,enum amdgpu_interrupt_state state)804a08f16cfSLeo (Hanghong) Ma static int amdgpu_dm_set_dmub_trace_irq_state(struct amdgpu_device *adev,
805a08f16cfSLeo (Hanghong) Ma struct amdgpu_irq_src *source,
806a08f16cfSLeo (Hanghong) Ma unsigned int type,
807a08f16cfSLeo (Hanghong) Ma enum amdgpu_interrupt_state state)
808a08f16cfSLeo (Hanghong) Ma {
809a08f16cfSLeo (Hanghong) Ma enum dc_irq_source irq_source = DC_IRQ_SOURCE_DMCUB_OUTBOX0;
810a08f16cfSLeo (Hanghong) Ma bool st = (state == AMDGPU_IRQ_STATE_ENABLE);
811a08f16cfSLeo (Hanghong) Ma
812a08f16cfSLeo (Hanghong) Ma dc_interrupt_set(adev->dm.dc, irq_source, st);
813a08f16cfSLeo (Hanghong) Ma return 0;
814a08f16cfSLeo (Hanghong) Ma }
815a08f16cfSLeo (Hanghong) Ma
8164562236bSHarry Wentland static const struct amdgpu_irq_src_funcs dm_crtc_irq_funcs = {
8174562236bSHarry Wentland .set = amdgpu_dm_set_crtc_irq_state,
8184562236bSHarry Wentland .process = amdgpu_dm_irq_handler,
8194562236bSHarry Wentland };
8204562236bSHarry Wentland
821320eca62SWayne Lin static const struct amdgpu_irq_src_funcs dm_vline0_irq_funcs = {
822320eca62SWayne Lin .set = amdgpu_dm_set_vline0_irq_state,
823320eca62SWayne Lin .process = amdgpu_dm_irq_handler,
824320eca62SWayne Lin };
825320eca62SWayne Lin
82681927e28SJude Shih static const struct amdgpu_irq_src_funcs dm_dmub_outbox_irq_funcs = {
82781927e28SJude Shih .set = amdgpu_dm_set_dmub_outbox_irq_state,
82881927e28SJude Shih .process = amdgpu_dm_irq_handler,
82981927e28SJude Shih };
83081927e28SJude Shih
831d2574c33SMario Kleiner static const struct amdgpu_irq_src_funcs dm_vupdate_irq_funcs = {
832d2574c33SMario Kleiner .set = amdgpu_dm_set_vupdate_irq_state,
833d2574c33SMario Kleiner .process = amdgpu_dm_irq_handler,
834d2574c33SMario Kleiner };
835d2574c33SMario Kleiner
836a08f16cfSLeo (Hanghong) Ma static const struct amdgpu_irq_src_funcs dm_dmub_trace_irq_funcs = {
837a08f16cfSLeo (Hanghong) Ma .set = amdgpu_dm_set_dmub_trace_irq_state,
838a08f16cfSLeo (Hanghong) Ma .process = amdgpu_dm_irq_handler,
839a08f16cfSLeo (Hanghong) Ma };
840a08f16cfSLeo (Hanghong) Ma
8414562236bSHarry Wentland static const struct amdgpu_irq_src_funcs dm_pageflip_irq_funcs = {
8424562236bSHarry Wentland .set = amdgpu_dm_set_pflip_irq_state,
8434562236bSHarry Wentland .process = amdgpu_dm_irq_handler,
8444562236bSHarry Wentland };
8454562236bSHarry Wentland
8464562236bSHarry Wentland static const struct amdgpu_irq_src_funcs dm_hpd_irq_funcs = {
8474562236bSHarry Wentland .set = amdgpu_dm_set_hpd_irq_state,
8484562236bSHarry Wentland .process = amdgpu_dm_irq_handler,
8494562236bSHarry Wentland };
8504562236bSHarry Wentland
amdgpu_dm_set_irq_funcs(struct amdgpu_device * adev)8514562236bSHarry Wentland void amdgpu_dm_set_irq_funcs(struct amdgpu_device *adev)
8524562236bSHarry Wentland {
853a83ccf7cSMikita Lipski adev->crtc_irq.num_types = adev->mode_info.num_crtc;
8544562236bSHarry Wentland adev->crtc_irq.funcs = &dm_crtc_irq_funcs;
8554562236bSHarry Wentland
856320eca62SWayne Lin adev->vline0_irq.num_types = adev->mode_info.num_crtc;
857320eca62SWayne Lin adev->vline0_irq.funcs = &dm_vline0_irq_funcs;
858320eca62SWayne Lin
85981927e28SJude Shih adev->dmub_outbox_irq.num_types = 1;
86081927e28SJude Shih adev->dmub_outbox_irq.funcs = &dm_dmub_outbox_irq_funcs;
86181927e28SJude Shih
862d2574c33SMario Kleiner adev->vupdate_irq.num_types = adev->mode_info.num_crtc;
863d2574c33SMario Kleiner adev->vupdate_irq.funcs = &dm_vupdate_irq_funcs;
864d2574c33SMario Kleiner
865a08f16cfSLeo (Hanghong) Ma adev->dmub_trace_irq.num_types = 1;
866a08f16cfSLeo (Hanghong) Ma adev->dmub_trace_irq.funcs = &dm_dmub_trace_irq_funcs;
867a08f16cfSLeo (Hanghong) Ma
868c8dd5715SMichel Dänzer adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
8694562236bSHarry Wentland adev->pageflip_irq.funcs = &dm_pageflip_irq_funcs;
8704562236bSHarry Wentland
871c8dd5715SMichel Dänzer adev->hpd_irq.num_types = adev->mode_info.num_hpd;
8724562236bSHarry Wentland adev->hpd_irq.funcs = &dm_hpd_irq_funcs;
8734562236bSHarry Wentland }
amdgpu_dm_outbox_init(struct amdgpu_device * adev)87481927e28SJude Shih void amdgpu_dm_outbox_init(struct amdgpu_device *adev)
87581927e28SJude Shih {
87681927e28SJude Shih dc_interrupt_set(adev->dm.dc,
87781927e28SJude Shih DC_IRQ_SOURCE_DMCUB_OUTBOX,
87881927e28SJude Shih true);
87981927e28SJude Shih }
8804562236bSHarry Wentland
881b8592b48SLeo Li /**
8824562236bSHarry Wentland * amdgpu_dm_hpd_init - hpd setup callback.
8834562236bSHarry Wentland *
8844562236bSHarry Wentland * @adev: amdgpu_device pointer
8854562236bSHarry Wentland *
8864562236bSHarry Wentland * Setup the hpd pins used by the card (evergreen+).
8874562236bSHarry Wentland * Enable the pin, set the polarity, and enable the hpd interrupts.
8884562236bSHarry Wentland */
amdgpu_dm_hpd_init(struct amdgpu_device * adev)8894562236bSHarry Wentland void amdgpu_dm_hpd_init(struct amdgpu_device *adev)
8904562236bSHarry Wentland {
8914a580877SLuben Tuikov struct drm_device *dev = adev_to_drm(adev);
8924562236bSHarry Wentland struct drm_connector *connector;
893f8d2d39eSLyude Paul struct drm_connector_list_iter iter;
8944562236bSHarry Wentland
895f8d2d39eSLyude Paul drm_connector_list_iter_begin(dev, &iter);
896f8d2d39eSLyude Paul drm_for_each_connector_iter(connector, &iter) {
897c84dec2fSHarry Wentland struct amdgpu_dm_connector *amdgpu_dm_connector =
898c84dec2fSHarry Wentland to_amdgpu_dm_connector(connector);
8994562236bSHarry Wentland
900c84dec2fSHarry Wentland const struct dc_link *dc_link = amdgpu_dm_connector->dc_link;
9014562236bSHarry Wentland
902*2d0b69fcSSrinivasan Shanmugam if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) {
9034562236bSHarry Wentland dc_interrupt_set(adev->dm.dc,
9044562236bSHarry Wentland dc_link->irq_source_hpd,
9054562236bSHarry Wentland true);
9064562236bSHarry Wentland }
9074562236bSHarry Wentland
908*2d0b69fcSSrinivasan Shanmugam if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {
9094562236bSHarry Wentland dc_interrupt_set(adev->dm.dc,
9104562236bSHarry Wentland dc_link->irq_source_hpd_rx,
9114562236bSHarry Wentland true);
9124562236bSHarry Wentland }
9134562236bSHarry Wentland }
914f8d2d39eSLyude Paul drm_connector_list_iter_end(&iter);
9154562236bSHarry Wentland }
9164562236bSHarry Wentland
9174562236bSHarry Wentland /**
9184562236bSHarry Wentland * amdgpu_dm_hpd_fini - hpd tear down callback.
9194562236bSHarry Wentland *
9204562236bSHarry Wentland * @adev: amdgpu_device pointer
9214562236bSHarry Wentland *
9224562236bSHarry Wentland * Tear down the hpd pins used by the card (evergreen+).
9234562236bSHarry Wentland * Disable the hpd interrupts.
9244562236bSHarry Wentland */
amdgpu_dm_hpd_fini(struct amdgpu_device * adev)9254562236bSHarry Wentland void amdgpu_dm_hpd_fini(struct amdgpu_device *adev)
9264562236bSHarry Wentland {
9274a580877SLuben Tuikov struct drm_device *dev = adev_to_drm(adev);
9284562236bSHarry Wentland struct drm_connector *connector;
929f8d2d39eSLyude Paul struct drm_connector_list_iter iter;
9304562236bSHarry Wentland
931f8d2d39eSLyude Paul drm_connector_list_iter_begin(dev, &iter);
932f8d2d39eSLyude Paul drm_for_each_connector_iter(connector, &iter) {
933c84dec2fSHarry Wentland struct amdgpu_dm_connector *amdgpu_dm_connector =
934c84dec2fSHarry Wentland to_amdgpu_dm_connector(connector);
935c84dec2fSHarry Wentland const struct dc_link *dc_link = amdgpu_dm_connector->dc_link;
9364562236bSHarry Wentland
937*2d0b69fcSSrinivasan Shanmugam if (dc_link->irq_source_hpd != DC_IRQ_SOURCE_INVALID) {
938d9db36d1SAlan Liu dc_interrupt_set(adev->dm.dc,
939d9db36d1SAlan Liu dc_link->irq_source_hpd,
940d9db36d1SAlan Liu false);
941d9db36d1SAlan Liu }
9424562236bSHarry Wentland
943*2d0b69fcSSrinivasan Shanmugam if (dc_link->irq_source_hpd_rx != DC_IRQ_SOURCE_INVALID) {
9444562236bSHarry Wentland dc_interrupt_set(adev->dm.dc,
9454562236bSHarry Wentland dc_link->irq_source_hpd_rx,
9464562236bSHarry Wentland false);
9474562236bSHarry Wentland }
9484562236bSHarry Wentland }
949f8d2d39eSLyude Paul drm_connector_list_iter_end(&iter);
9504562236bSHarry Wentland }
951