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/openbmc/u-boot/drivers/clk/
H A Dclk_meson.c2fa77bd1 Tue Nov 13 04:38:38 CST 2018 Jerome Brunet <jbrunet@baylibre.com> clk: meson: fix clk81 divider calculation

clk81 divider is 0 based (meaning that 0 value in the register means
divide by 1). Fix clk81 rate calculation for this.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>