Searched hist:"2 ecf1726" (Results 1 – 6 of 6) sorted by relevance
| /openbmc/qemu/hw/misc/ |
| H A D | aspeed_lpc.c | 2ecf1726 Tue Mar 09 05:01:28 CST 2021 Cédric Le Goater <clg@kaod.org> hw/misc: Add a basic Aspeed LPC controller model
This is a very minimal framework to access registers which are used to
configure the AHB memory mapping of the flash chips on the LPC HC
Firmware address space.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Message-Id: <20210302014317.915120-5-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
|
| H A D | meson.build | 2ecf1726 Tue Mar 09 05:01:28 CST 2021 Cédric Le Goater <clg@kaod.org> hw/misc: Add a basic Aspeed LPC controller model
This is a very minimal framework to access registers which are used to
configure the AHB memory mapping of the flash chips on the LPC HC
Firmware address space.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Message-Id: <20210302014317.915120-5-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
|
| /openbmc/qemu/include/hw/misc/ |
| H A D | aspeed_lpc.h | 2ecf1726 Tue Mar 09 05:01:28 CST 2021 Cédric Le Goater <clg@kaod.org> hw/misc: Add a basic Aspeed LPC controller model
This is a very minimal framework to access registers which are used to
configure the AHB memory mapping of the flash chips on the LPC HC
Firmware address space.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Message-Id: <20210302014317.915120-5-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
|
| /openbmc/qemu/docs/system/arm/ |
| H A D | aspeed.rst | 2ecf1726 Tue Mar 09 05:01:28 CST 2021 Cédric Le Goater <clg@kaod.org> hw/misc: Add a basic Aspeed LPC controller model
This is a very minimal framework to access registers which are used to
configure the AHB memory mapping of the flash chips on the LPC HC
Firmware address space.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Message-Id: <20210302014317.915120-5-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
|
| /openbmc/qemu/hw/arm/ |
| H A D | aspeed_ast2600.c | 2ecf1726 Tue Mar 09 05:01:28 CST 2021 Cédric Le Goater <clg@kaod.org> hw/misc: Add a basic Aspeed LPC controller model
This is a very minimal framework to access registers which are used to
configure the AHB memory mapping of the flash chips on the LPC HC
Firmware address space.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Message-Id: <20210302014317.915120-5-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
|
| /openbmc/qemu/include/hw/arm/ |
| H A D | aspeed_soc.h | 2ecf1726 Tue Mar 09 05:01:28 CST 2021 Cédric Le Goater <clg@kaod.org> hw/misc: Add a basic Aspeed LPC controller model
This is a very minimal framework to access registers which are used to
configure the AHB memory mapping of the flash chips on the LPC HC
Firmware address space.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Message-Id: <20210302014317.915120-5-andrew@aj.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
|