Searched hist:"2 de40f68" (Results 1 – 3 of 3) sorted by relevance
| /openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/ |
| H A D | dr_ste_v1.c | 2de40f68 Sun Jun 27 15:05:28 CDT 2021 Yevgeny Kliteynik <kliteyn@nvidia.com> net/mlx5: DR, Enable VLAN pop on TX and VLAN push on RX
Enable pop VLAN action in TX and push VLAN in RX.
These actions are supported only on STEv1.
On TX: when a host sends a packet, VLAN is popped at the beginning.
On RX: just before passing the packet to the host the VLAN is pushed.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com>
Signed-off-by: Alex Vesker <valex@nvidia.com>
Signed-off-by: Yishai Hadas <yishaih@nvidia.com>
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
|
| H A D | dr_action.c | 2de40f68 Sun Jun 27 15:05:28 CDT 2021 Yevgeny Kliteynik <kliteyn@nvidia.com> net/mlx5: DR, Enable VLAN pop on TX and VLAN push on RX
Enable pop VLAN action in TX and push VLAN in RX.
These actions are supported only on STEv1.
On TX: when a host sends a packet, VLAN is popped at the beginning.
On RX: just before passing the packet to the host the VLAN is pushed.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com>
Signed-off-by: Alex Vesker <valex@nvidia.com>
Signed-off-by: Yishai Hadas <yishaih@nvidia.com>
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
|
| H A D | dr_types.h | 2de40f68 Sun Jun 27 15:05:28 CDT 2021 Yevgeny Kliteynik <kliteyn@nvidia.com> net/mlx5: DR, Enable VLAN pop on TX and VLAN push on RX
Enable pop VLAN action in TX and push VLAN in RX.
These actions are supported only on STEv1.
On TX: when a host sends a packet, VLAN is popped at the beginning.
On RX: just before passing the packet to the host the VLAN is pushed.
Signed-off-by: Muhammad Sammar <muhammads@nvidia.com>
Signed-off-by: Alex Vesker <valex@nvidia.com>
Signed-off-by: Yishai Hadas <yishaih@nvidia.com>
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
|