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/openbmc/u-boot/arch/arm/include/asm/
H A Dutils.h2c451f7831208741d0ff7ca6046cffcd9ee49def Thu Jun 16 18:30:47 CDT 2011 Aneesh V <aneesh@ti.com> armv7: cache maintenance operations for armv7

- Add a framework for layered cache maintenance
- separate out SOC specific outer cache maintenance from
maintenance of caches known to CPU

- Add generic ARMv7 cache maintenance operations that affect all
caches known to ARMv7 CPUs. For instance in Cortex-A8 these
opertions will affect both L1 and L2 caches. In Cortex-A9
these will affect only L1 cache

- D-cache operations supported:
- Invalidate entire D-cache
- Invalidate D-cache range
- Flush(clean & invalidate) entire D-cache
- Flush D-cache range
- I-cache operations supported:
- Invalidate entire I-cache

- Add maintenance functions for TLB, branch predictor array etc.

- Enable -march=armv7-a so that armv7 assembly instructions can be
used

Signed-off-by: Aneesh V <aneesh@ti.com>
H A Darmv7.h2c451f7831208741d0ff7ca6046cffcd9ee49def Thu Jun 16 18:30:47 CDT 2011 Aneesh V <aneesh@ti.com> armv7: cache maintenance operations for armv7

- Add a framework for layered cache maintenance
- separate out SOC specific outer cache maintenance from
maintenance of caches known to CPU

- Add generic ARMv7 cache maintenance operations that affect all
caches known to ARMv7 CPUs. For instance in Cortex-A8 these
opertions will affect both L1 and L2 caches. In Cortex-A9
these will affect only L1 cache

- D-cache operations supported:
- Invalidate entire D-cache
- Invalidate D-cache range
- Flush(clean & invalidate) entire D-cache
- Flush D-cache range
- I-cache operations supported:
- Invalidate entire I-cache

- Add maintenance functions for TLB, branch predictor array etc.

- Enable -march=armv7-a so that armv7 assembly instructions can be
used

Signed-off-by: Aneesh V <aneesh@ti.com>
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dcache_v7.c2c451f7831208741d0ff7ca6046cffcd9ee49def Thu Jun 16 18:30:47 CDT 2011 Aneesh V <aneesh@ti.com> armv7: cache maintenance operations for armv7

- Add a framework for layered cache maintenance
- separate out SOC specific outer cache maintenance from
maintenance of caches known to CPU

- Add generic ARMv7 cache maintenance operations that affect all
caches known to ARMv7 CPUs. For instance in Cortex-A8 these
opertions will affect both L1 and L2 caches. In Cortex-A9
these will affect only L1 cache

- D-cache operations supported:
- Invalidate entire D-cache
- Invalidate D-cache range
- Flush(clean & invalidate) entire D-cache
- Flush D-cache range
- I-cache operations supported:
- Invalidate entire I-cache

- Add maintenance functions for TLB, branch predictor array etc.

- Enable -march=armv7-a so that armv7 assembly instructions can be
used

Signed-off-by: Aneesh V <aneesh@ti.com>
H A DMakefile2c451f7831208741d0ff7ca6046cffcd9ee49def Thu Jun 16 18:30:47 CDT 2011 Aneesh V <aneesh@ti.com> armv7: cache maintenance operations for armv7

- Add a framework for layered cache maintenance
- separate out SOC specific outer cache maintenance from
maintenance of caches known to CPU

- Add generic ARMv7 cache maintenance operations that affect all
caches known to ARMv7 CPUs. For instance in Cortex-A8 these
opertions will affect both L1 and L2 caches. In Cortex-A9
these will affect only L1 cache

- D-cache operations supported:
- Invalidate entire D-cache
- Invalidate D-cache range
- Flush(clean & invalidate) entire D-cache
- Flush D-cache range
- I-cache operations supported:
- Invalidate entire I-cache

- Add maintenance functions for TLB, branch predictor array etc.

- Enable -march=armv7-a so that armv7 assembly instructions can be
used

Signed-off-by: Aneesh V <aneesh@ti.com>
/openbmc/u-boot/include/
H A Dcommon.h2c451f7831208741d0ff7ca6046cffcd9ee49def Thu Jun 16 18:30:47 CDT 2011 Aneesh V <aneesh@ti.com> armv7: cache maintenance operations for armv7

- Add a framework for layered cache maintenance
- separate out SOC specific outer cache maintenance from
maintenance of caches known to CPU

- Add generic ARMv7 cache maintenance operations that affect all
caches known to ARMv7 CPUs. For instance in Cortex-A8 these
opertions will affect both L1 and L2 caches. In Cortex-A9
these will affect only L1 cache

- D-cache operations supported:
- Invalidate entire D-cache
- Invalidate D-cache range
- Flush(clean & invalidate) entire D-cache
- Flush D-cache range
- I-cache operations supported:
- Invalidate entire I-cache

- Add maintenance functions for TLB, branch predictor array etc.

- Enable -march=armv7-a so that armv7 assembly instructions can be
used

Signed-off-by: Aneesh V <aneesh@ti.com>
/openbmc/u-boot/
H A DREADME2c451f7831208741d0ff7ca6046cffcd9ee49def Thu Jun 16 18:30:47 CDT 2011 Aneesh V <aneesh@ti.com> armv7: cache maintenance operations for armv7

- Add a framework for layered cache maintenance
- separate out SOC specific outer cache maintenance from
maintenance of caches known to CPU

- Add generic ARMv7 cache maintenance operations that affect all
caches known to ARMv7 CPUs. For instance in Cortex-A8 these
opertions will affect both L1 and L2 caches. In Cortex-A9
these will affect only L1 cache

- D-cache operations supported:
- Invalidate entire D-cache
- Invalidate D-cache range
- Flush(clean & invalidate) entire D-cache
- Flush D-cache range
- I-cache operations supported:
- Invalidate entire I-cache

- Add maintenance functions for TLB, branch predictor array etc.

- Enable -march=armv7-a so that armv7 assembly instructions can be
used

Signed-off-by: Aneesh V <aneesh@ti.com>