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| /openbmc/linux/drivers/clk/microchip/ |
| H A D | clk-mpfs.c | 14016e4a Fri Sep 09 07:31:17 CDT 2022 Conor Dooley <conor.dooley@microchip.com> clk: microchip: mpfs: add MSS pll's set & round rate
The MSS pll is not a fixed frequency clock, so add set() & round_rate()
support.
Control is limited to a 7 bit output divider as other devices on the
FPGA occupy the other three outputs of the PLL & prevent changing
the multiplier.
Reviewed-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220909123123.2699583-9-conor.dooley@microchip.com
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