Home
last modified time | relevance | path

Searched hist:"0678587 fb6f517d40c461f1d43fe7a6ff430f168" (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dstart.S0678587fb6f517d40c461f1d43fe7a6ff430f168 Tue Feb 26 06:28:27 CST 2013 Stephen Warren <swarren@nvidia.com> ARM: implement some Cortex-A9 errata workarounds

Various errata exist in the Cortex-A9 CPU, and may be worked around by
setting some bits in a CP15 diagnostic register. Add code to implement
the workarounds, enabled by new CONFIG_ options.

This code was taken from the Linux kernel, v3.8, arch/arm/mm/proc-v7.S,
and modified to remove the logic to conditionally apply the WAR (since we
know exactly which CPU we're running on given the U-Boot configuration),
and use r0 instead of r10 for consistency with the rest of U-Boot's
cpu_init_cp15().

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
/openbmc/u-boot/
H A DREADME0678587fb6f517d40c461f1d43fe7a6ff430f168 Tue Feb 26 06:28:27 CST 2013 Stephen Warren <swarren@nvidia.com> ARM: implement some Cortex-A9 errata workarounds

Various errata exist in the Cortex-A9 CPU, and may be worked around by
setting some bits in a CP15 diagnostic register. Add code to implement
the workarounds, enabled by new CONFIG_ options.

This code was taken from the Linux kernel, v3.8, arch/arm/mm/proc-v7.S,
and modified to remove the logic to conditionally apply the WAR (since we
know exactly which CPU we're running on given the U-Boot configuration),
and use r0 instead of r10 for consistency with the rest of U-Boot's
cpu_init_cp15().

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>