Searched hist:"03 abfd90" (Results 1 – 4 of 4) sorted by relevance
| /openbmc/qemu/target/ppc/ |
| H A D | cpu_init.c | 03abfd90 Thu May 19 08:59:08 CDT 2022 Nicholas Piggin <npiggin@gmail.com> target/ppc: Implement lwsync with weaker memory ordering
This allows an x86 host to no-op lwsyncs, and ppc host can use lwsync
rather than sync.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220519135908.21282-5-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
|
| H A D | machine.c | 03abfd90 Thu May 19 08:59:08 CDT 2022 Nicholas Piggin <npiggin@gmail.com> target/ppc: Implement lwsync with weaker memory ordering
This allows an x86 host to no-op lwsyncs, and ppc host can use lwsync
rather than sync.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220519135908.21282-5-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
|
| H A D | translate.c | 03abfd90 Thu May 19 08:59:08 CDT 2022 Nicholas Piggin <npiggin@gmail.com> target/ppc: Implement lwsync with weaker memory ordering
This allows an x86 host to no-op lwsyncs, and ppc host can use lwsync
rather than sync.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220519135908.21282-5-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
|
| H A D | cpu.h | 03abfd90 Thu May 19 08:59:08 CDT 2022 Nicholas Piggin <npiggin@gmail.com> target/ppc: Implement lwsync with weaker memory ordering
This allows an x86 host to no-op lwsyncs, and ppc host can use lwsync
rather than sync.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220519135908.21282-5-npiggin@gmail.com>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
|