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Searched +full:zynq +full:- +full:spi +full:- +full:r1p6 (Results 1 – 8 of 8) sorted by relevance

/openbmc/u-boot/doc/device-tree-bindings/spi/
H A Dspi-zynq.txt1 Cadence SPI controller Device Tree Bindings
2 -------------------------------------------
5 - compatible : Should be "cdns,spi-r1p6" or "xlnx,zynq-spi-r1p6".
6 - reg : Physical base address and size of SPI registers map.
7 - interrupts : Property with a value describing the interrupt
9 - interrupt-parent : Must be core interrupt controller
10 - clock-names : List of input clock names - "ref_clk", "pclk"
12 - clocks : Clock phandles (see clock bindings for details).
13 - spi-max-frequency : Maximum SPI clocking speed of device in Hz
16 - num-cs : Number of chip selects used.
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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dspi-cadence.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-cadence.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence SPI controller
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: spi-controller.yaml#
18 - cdns,spi-r1p6
19 - xlnx,zynq-spi-r1p6
27 clock-names:
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/openbmc/u-boot/drivers/spi/
H A Dzynq_spi.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Xilinx Zynq PS SPI controller driver (master mode only)
12 #include <spi.h>
17 /* zynq spi register bit masks ZYNQ_SPI_<REG>_<BIT>_MASK */
28 #define ZYNQ_SPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
39 /* zynq spi register set */
53 /* zynq spi platform data */
62 /* zynq spi priv */
74 struct zynq_spi_platdata *plat = bus->platdata; in zynq_spi_ofdata_to_platdata()
75 const void *blob = gd->fdt_blob; in zynq_spi_ofdata_to_platdata()
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/openbmc/u-boot/arch/arm/dts/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * Xilinx Zynq 7000 DTSI
4 * Describes the hardware common to all Zynq 7000-based boards.
6 * Copyright (C) 2011 - 2015 Xilinx
10 #address-cells = <1>;
11 #size-cells = <1>;
12 compatible = "xlnx,zynq-7000";
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
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H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2015, Xilinx, Inc.
17 #address-cells = <2>;
18 #size-cells = <2>;
21 #address-cells = <1>;
22 #size-cells = <0>;
25 compatible = "arm,cortex-a53", "arm,armv8";
27 enable-method = "psci";
28 operating-points-v2 = <&cpu_opp_table>;
30 cpu-idle-states = <&CPU_SLEEP_0>;
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/openbmc/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
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/openbmc/linux/drivers/spi/
H A Dspi-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Cadence SPI controller driver (host and target mode)
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
21 #include <linux/spi/spi.h>
24 #define CDNS_SPI_NAME "cdns-spi"
41 * SPI Configuration Register bit Masks
44 * of the SPI controller
62 * SPI Configuration Register - Baud rate and target select
76 * SPI Interrupt Registers bit Masks
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/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2014 - 2021, Xilinx, Inc.
15 #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/interrupt-controller/arm-gic.h>
18 #include <dt-bindings/interrupt-controller/irq.h>
19 #include <dt-bindings/power/xlnx-zynqmp-power.h>
20 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
24 #address-cells = <2>;
25 #size-cells = <2>;
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