| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Sensor/ |
| H A D | Type.interface.yaml | 8 - name: ReadingBasis
12 - readonly
14 Defines the type of the sensor based on how the sensor reading is
17 - name: Implementation
21 - readonly
27 - name: ReadingBasisType
29 Types of the sensors based on how their reading is determined.
31 - name: Unknown
35 - name: Zero
37 A zero-based reading. This value shall indicate a reading with
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| /openbmc/u-boot/arch/arm/mach-bcm283x/ |
| H A D | Kconfig | 17 bool "Broadcom BCM2837 SoC 32-bit support"
24 bool "Broadcom BCM2837 SoC 64-bit support"
39 Support for all ARM1176-/BCM2835-based Raspberry Pi variants, such as
40 the A, A+, B, B+, Compute Module, and Zero. This option cannot
41 support BCM2836/BCM2837-based Raspberry Pis such as the RPi 2 and
48 bool "Raspberry Pi Zero W"
50 Support for all ARM1176-/BCM2835-based Raspberry Pi variants, such as
51 the RPi Zero model W.
55 default on the RPi Zero W. To enable the UART console, the following
56 non-default option must be present in config.txt: enable_uart=1.
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| /openbmc/qemu/docs/ |
| H A D | xbzrle.txt | 1 XBZRLE (Xor Based Zero Run Length Encoding)
4 Using XBZRLE (Xor Based Zero Run Length Encoding) allows for the reduction
5 of VM downtime and the total live-migration time of Virtual machines.
26 of the page, where zero represents an unchanged value.
27 The page data delta is represented by zero and non zero runs.
28 A zero run is represented by its length (in bytes).
29 A non zero run is represented by its length (in bytes) and the new data.
49 This work was originally based on research results published
55 XBZRLE has a sustained bandwidth of 2-2.5 GB/s for typical workloads making it
56 ideal for in-line, real-time encoding such as is needed for live-migration.
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| /openbmc/u-boot/board/imgtec/malta/ |
| H A D | lowlevel_init.S | 1 /* SPDX-License-Identifier: GPL-2.0 */
53 * based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com>
56 * 'MIPS: qemu-malta: add YAMON-style GT64120 memory map'
58 * http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html
60 * based on write_bootloader() in qemu.git/hw/mips_malta.c
69 /* setup MEM-to-PCI0 mapping */
72 /* setup PCI0 io window to 0x18000000-0x181fffff */
121 li t2, -CONFIG_SYS_MEM_SIZE
127 /* initialise IP1 - unused */
129 li t2, -MALTA_MSC01_IP1_SIZE
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| /openbmc/qemu/scripts/kvm/ |
| H A D | vmxcap | 5 # Copyright 2009-2010 Red Hat, Inc.
11 # the COPYING file in the top-level directory.
60 zero = not (mb1 & (1 << bit))
66 and one and not zero):
68 elif zero and not one:
70 elif one and not zero:
72 elif one and zero:
74 print(' %-40s %s' % (self.bits[bit], s))
76 # All 64 bits in the tertiary controls MSR are allowed-1
105 v = (value >> lo) & ((1 << (hi - lo + 1)) - 1)
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| /openbmc/u-boot/board/Seagate/goflexhome/ |
| H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
5 # Based on dockstar/kwbimage.cfg originally written by
8 # Based on sheevaplug/kwbimage.cfg originally written by
12 # Refer docs/README.kwimage for more details about how-to configure
24 # Configure RGMII-0 interface pad voltage to 1.8V
29 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
30 # bit23-14: zero
33 # bit29-26: zero
34 # bit31-30: 01
42 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
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| /openbmc/qemu/include/hw/ |
| H A D | ptimer.h | 19 * When it reaches zero it will trigger a callback function, and
21 * and keep counting down, or to stop (as a one-shot timer).
23 * A transaction-based API is used for modifying ptimer state: all calls
29 * list of state-modifying functions and detailed semantics of the callback.)
31 * Forgetting to set the period/frequency (or setting it to zero) is a
49 * - Starting to run with a period = 0 emits error message and stops the
52 * - Setting period to 0 of the running timer emits error message and
55 * - Starting to run with counter = 0 or setting it to "0" while timer
59 * - Counter value of the running timer is one less than the actual value.
61 * - Changing period/frequency of the running timer loses time elapsed
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| /openbmc/u-boot/doc/imx/common/ |
| H A D | mxs.txt | 1 Booting U-Boot on a MXS processor
4 This document describes the MXS U-Boot port. This document mostly covers topics
8 -----------
14 into the unix command prompt in U-Boot source code root directory.
16 The (=>) introduces a snipped of code that should by typed into U-Boot command
20 --------
23 2) Compiling U-Boot for a MXS based board
24 3) Installation of U-Boot for a MXS based board to SD card
25 4) Installation of U-Boot into NAND flash on a MX28 based board
26 5) Installation of U-Boot into SPI NOR flash on a MX28 based board
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| /openbmc/qemu/target/i386/tcg/ |
| H A D | decode-new.h | 2 * Decode table flags, mostly based on Intel SDM.
35 X86_TYPE_L, /* The upper 4 bits of the immediate select a 128-bit register */
52 X86_TYPE_I_unsigned, /* Immediate, zero-extended */
53 X86_TYPE_nop, /* modrm operand decoded but not loaded into s->T{0,1} */
54 X86_TYPE_2op, /* 2-operand RMW instruction */
55 X86_TYPE_LoBits, /* encoded in bits 0-2 of the operand + REX.B */
56 X86_TYPE_0, /* Hard-coded GPRs (RAX..RDI) */
64 X86_TYPE_ES, /* Hard-coded segment registers */
77 X86_SIZE_d, /* 32-bit */
78 X86_SIZE_dq, /* SSE/AVX 128-bit */
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| /openbmc/u-boot/include/ |
| H A D | dma.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright (C) 2015 - 2018 Texas Instruments Incorporated <www.ti.com>
16 * enum dma_direction - dma transfer direction indicator
35 * struct dma_dev_priv - information about a device used by the uclass
61 * DMA consumer DMA_MEM_TO_DEV (transmit) usage example (based on networking).
62 * Note. dma_send() is sync operation always - it'll start transfer and will
64 * - get/request dma channel
66 * ret = dma_get_by_name(common->dev, "tx0", &dma_tx);
69 * - enable dma channel
73 * - dma transmit DMA_MEM_TO_DEV.
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | sun8i-h2-plus-bananapi-m2-zero.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Based on sun8i-h3-bananapi-m2-plus.dts, which is:
6 * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
9 /dts-v1/;
10 #include "sun8i-h3.dtsi"
11 #include "sunxi-common-regulators.dtsi"
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/input/input.h>
17 model = "Banana Pi BPI-M2-Zero";
18 compatible = "sinovoip,bpi-m2-zero", "allwinner,sun8i-h2-plus";
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| H A D | sun8i-h2-plus-orangepi-r1.dts | 4 * This file is dual-licensed: you can use it either under the terms
43 /* Orange Pi R1 is based on Orange Pi Zero design */
44 #include "sun8i-h2-plus-orangepi-zero.dts"
48 compatible = "xunlong,orangepi-r1", "allwinner,sun8i-h2-plus";
50 /delete-node/ reg_vcc_wifi;
53 * Ths pin of this regulator is the same with the Wi-Fi extra
54 * regulator on the original Zero. However it's used for USB
55 * Ethernet rather than the Wi-Fi now.
57 reg_vcc_usb_eth: reg-vcc-usb-ethernet {
58 compatible = "regulator-fixed";
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| /openbmc/docs/designs/ |
| H A D | multihost-phosphor-buttons.md | 1 # Multi-host front panel phosphor buttons interface
15 phosphor-buttons currently only support push type buttons.support for different
20 Currently handler events are only based on monitoring gpio events as input
23 based on dbus property changes.
38 +----------------------------------------------+
42 | +--------------+ +--------------+ |
46 | +--------------+ +--------------+ |
51 +----------------------------------------------+
57 example for a multihost platform yosemite-V2 it has host selector switch mux as
61 +---------------------------+ +------------+
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| /openbmc/u-boot/board/gateworks/gw_ventana/ |
| H A D | README | 1 U-Boot for the Gateworks Ventana Product Family boards
3 This file contains information for the port of U-Boot to the Gateworks
7 is supported by a single bootloader build by using a common SPL and U-Boot
13 ---------------------------------
19 will build the following artifacts from U-Boot source:
20 - SPL - Secondary Program Loader that the i.MX6 BOOT ROM (Primary Program
22 The DRAM controller, loads u-boot.img from the detected boot device,
25 - u-boot.img - The main U-Boot core which is u-boot.bin with a image header.
29 --------
31 To build U-Boot for the Gateworks Ventana product family:
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| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/ |
| H A D | ObjectMapper.interface.yaml | 8 - name: GetObject
10 Obtain a dictionary of service -> implemented interface(s) for the
13 - name: path
17 - name: interfaces
22 - name: services
25 A dictionary of service -> implemented interface(s).
27 - xyz.openbmc_project.Common.Error.ResourceNotFound
28 - name: GetAncestors
30 Obtain a dictionary of ancestor -> services where ancestor is an
34 - name: path
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| /openbmc/u-boot/arch/xtensa/include/asm/ |
| H A D | byteorder.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Based on Linux/Xtensa kernel version
5 * Copyright (C) 2001 - 2007 Tensilica Inc.
33 * we cannot assume that the upper 16-bits of the register are in ___arch__swab16()
34 * zero. We are careful to mask values after shifting. in ___arch__swab16()
38 * There exists an anomaly between xt-gcc and xt-xcc. xt-gcc in ___arch__swab16()
40 * to ensure that it uses only the least-significant 16 bits of in ___arch__swab16()
41 * the result. xt-xcc doesn't use an extui, but assumes the in ___arch__swab16()
43 * 'unsigned short' result are still zero. This macro doesn't in ___arch__swab16()
47 * Declaring the temporary variables 'res' and 'tmp' to be 32-bit in ___arch__swab16()
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| /openbmc/u-boot/board/Seagate/nas220/ |
| H A D | kwbimage.cfg | 2 # Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com>
4 # Based on sheevaplug/kwbimage.cfg originally written by
9 # SPDX-License-Identifier: GPL-2.0+
11 # Refer doc/README.kwbimage for more details about how-to configure
23 # Configure RGMII-0 interface pad voltage to 1.8V
28 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
29 # bit23-14: zero
32 # bit29-26: zero
33 # bit31-30: 01
41 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
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| /openbmc/libcper/generator/sections/ |
| H A D | gen-section-ia32x64.c | 2 * Functions for generating pseudo-random CPER IA32/x64 sections.
10 #include <libcper/generator/gen-utils.h>
11 #include <libcper/generator/sections/gen-section.h>
17 //Generates a single pseudo-random IA32/x64 section, saving the resulting address to the given
90 //Set error structure reserved space to zero. in generate_ia32x64_error_structure()
109 //Set reserved space to zero. in generate_ia32x64_error_structure()
119 //Set reserved space to zero. in generate_ia32x64_error_structure()
129 //Set reserved space to zero. in generate_ia32x64_error_structure()
139 //Set reserved space to zero. in generate_ia32x64_error_structure()
151 //Initial length is 16 bytes. Add extra based on type. in generate_ia32x64_context_structure()
|
| /openbmc/phosphor-logging/extensions/openpower-pels/ |
| H A D | log_id.hpp | 17 * @param[in] id - the ID to add it to
19 * @return - the full log ID
24 * @brief Generates a PEL ID based on the current time.
43 * @return uint32_t - The log ID
48 * @brief Check for file containing zero data.
|
| /openbmc/u-boot/drivers/mmc/ |
| H A D | mmc_boot.c | 1 // SPDX-License-Identifier: GPL-2.0+
80 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
95 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
112 mmc->part_config = part_conf; in mmc_set_part_conf()
118 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
119 * for enable. Note that this is a write-once field for non-zero values.
|
| /openbmc/qemu/tests/uefi-test-tools/UefiTestToolsPkg/Include/Guid/ |
| H A D | BiosTablesTest.h | 3 point(s) in a MB-aligned structure to the hypervisor.
5 The hypervisor locates the MB-aligned structure based on the signature GUID
18 <http://opensource.org/licenses/bsd-license.php>.
46 // The signature GUID is written to the MB-aligned structure from
50 // bit-flipping occurs in order not to store the actual GUID in any UEFI
57 // Rsdp10 is the guest-physical address of the ACPI 1.0 specification RSD PTR
58 // table, in 8-byte little endian representation. Rsdp20 is the same, for the
60 // zero (independently of the other) if the UEFI System Table does not
67 // matches. Smbios21 is the guest-physical address of the SMBIOS 2.1 (32-bit)
68 // Entry Point Structure from the SMBIOS v3.2.0 specification, in 8-byte
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| /openbmc/qemu/common-user/host/loongarch64/ |
| H A D | safe-syscall.inc.S | 2 * safe-syscall.inc.S : host-specific assembly fragment
4 * This is intended to be included by common-user/safe-syscall.S
8 * Based on safe-syscall.inc.S code for RISC-V,
13 * See the COPYING file in the top-level directory.
72 /* If signal_pending is non-zero, don't do the call */
78 li.w $t2, -4096
83 0: sub.d $a0, $zero, $a0
90 .size safe_syscall_base, .-safe_syscall_base
|
| /openbmc/u-boot/board/LaCie/netspace_v2/ |
| H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
5 # Based on Kirkwood support:
8 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
9 # Refer doc/README.kwbimage for more details about how-to configure
19 # Configure RGMII-0 interface pad voltage to 1.8V
24 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
25 # bit23-14: zero
28 # bit29-26: zero
29 # bit31-30: 01
37 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
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| H A D | kwbimage-is2.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
5 # Based on Kirkwood support:
8 # Written-by: Prafulla Wadaskar <prafulla@marvell.com>
9 # Refer doc/README.kwbimage for more details about how-to configure
19 # Configure RGMII-0 interface pad voltage to 1.8V
24 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
25 # bit23-14: zero
28 # bit29-26: zero
29 # bit31-30: 01
37 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
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| /openbmc/u-boot/board/cloudengines/pogo_e02/ |
| H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+
6 # Based on Kirkwood support:
9 # Written-by: Prafulla Wadaskar <prafulla <at> marvell.com>
10 # Refer doc/README.kwbimage for more details about how-to configure
22 # Configure RGMII-0 interface pad voltage to 1.8V
27 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
28 # bit23-14: zero
31 # bit29-26: zero
32 # bit31-30: 01
40 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
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|