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/openbmc/u-boot/doc/device-tree-bindings/serial/
H A Dxilinx_uartlite.txt1 Binding for Xilinx Uartlite Controller
4 - compatible : should be "xlnx,xps-uartlite-1.00.a", or "xlnx,opb-uartlite-1.00.b"
5 - reg: Should contain UART controller registers location and length.
6 - interrupts: Should contain UART controller interrupts.
10 compatible = "xlnx,xps-uartlite-1.00.a";
11 interrupts = <1 0>;
/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dxlnx,opb-uartlite.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/serial/xlnx,opb-uartlite.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Axi Uartlite
10 - Peter Korsgaard <jacmet@sunsite.dk>
16 - xlnx,xps-uartlite-1.00.a
17 - xlnx,opb-uartlite-1.00.b
20 maxItems: 1
23 maxItems: 1
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/openbmc/u-boot/drivers/serial/
H A Dserial_xuartlite.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2008 - 2015 Michal Simek <monstr@monstr.eu>
7 * Yasushi SHOJI <yashi@atmark-techno.com>
20 #define SR_RX_FIFO_FULL BIT(1) /* receive FIFO full */
25 struct uartlite { struct
33 struct uartlite *regs; argument
39 struct uartlite *regs = plat->regs; in uartlite_serial_putc()
41 if (in_be32(&regs->status) & SR_TX_FIFO_FULL) in uartlite_serial_putc()
42 return -EAGAIN; in uartlite_serial_putc()
44 out_be32(&regs->tx_fifo, ch & 0xff); in uartlite_serial_putc()
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/openbmc/linux/Documentation/devicetree/bindings/
H A Dxilinx.txt10 Each IP-core has a set of parameters which the FPGA designer can use to
20 properties of the device node. In general, device nodes for IP-cores
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 interrupt-parent = <&interrupt-controller-phandle>;
29 xlnx,(parameter1) = "(string-value)";
30 xlnx,(parameter2) = <(int-value)>;
33 (generic-name): an open firmware-style name that describes the
36 (ip-core-name): the name of the ip block (given after the BEGIN
38 and all underscores '_' converted to dashes '-'.
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/openbmc/linux/drivers/tty/serial/
H A Duartlite.c1 // SPDX-License-Identifier: GPL-2.0
3 * uartlite.c: Serial driver for Xilinx uartlite serial controller
31 /* ---------------------------------------------------------------------
115 struct uartlite_data *pdata = port->private_data; in uart_in32()
117 return pdata->reg_ops->in(port->membase + offset); in uart_in32()
122 struct uartlite_data *pdata = port->private_data; in uart_out32()
124 pdata->reg_ops->out(val, port->membase + offset); in uart_out32()
131 /* ---------------------------------------------------------------------
137 struct tty_port *tport = &port->state->port; in ulite_receive()
147 port->icount.rx++; in ulite_receive()
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/openbmc/linux/arch/sh/boot/dts/
H A Dj2_mimas_v2.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 compatible = "jcore,j2-soc";
8 #address-cells = <1>;
9 #size-cells = <1>;
11 interrupt-parent = <&aic>;
14 #address-cells = <1>;
15 #size-cells = <0>;
21 clock-frequency = <50000000>;
22 d-cache-size = <8192>;
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/openbmc/qemu/hw/char/
H A Dxilinx_uartlite.c2 * QEMU model of Xilinx uartlite.
29 #include "hw/qdev-properties.h"
30 #include "hw/qdev-properties-system.h"
33 #include "chardev/char-fe.h"
39 #define R_TX 1
75 if (s->rx_fifo_len) in uart_update_irq()
76 s->regs[R_STATUS] |= STATUS_IE; in uart_update_irq()
78 irq = (s->regs[R_STATUS] & STATUS_IE) && (s->regs[R_CTRL] & CONTROL_IE); in uart_update_irq()
79 qemu_set_irq(s->irq, irq); in uart_update_irq()
86 r = s->regs[R_STATUS]; in uart_update_status()
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/openbmc/qemu/pc-bios/
H A Dpetalogix-s3adsp1800.dts5 * SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
11 #address-cells = <0x01>;
12 #size-cells = <0x01>;
23 stdout-path = "/plb/serial@84000000";
27 #address-cells = <0x01>;
28 #size-cells = <0x00>;
32 clock-frequency = <0x3b9aca0>;
33 compatible = "xlnx,microblaze-7.10.d";
34 d-cache-baseaddr = <0x90000000>;
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/openbmc/linux/arch/microblaze/boot/dts/
H A Dsystem.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * (C) Copyright 2007-2008 Xilinx, Inc.
6 * (C) Copyright 2007-2009 Michal Simek
13 * XPS project directory: Xilinx-ML505-ll_temac-sgdma-MMU-FDT-edk101
16 /dts-v1/;
18 #address-cells = <1>;
19 #size-cells = <1>;
32 stdout-path = "/plb@0/serial@84000000";
35 #address-cells = <1>;
37 #size-cells = <0>;
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/openbmc/linux/
H A DMAINTAINERS5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-scsi@vger.kernel.org
88 F: drivers/scsi/3w-*
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H A Dopengrok2.0.log1 2024-12-28 20:05:26.116-0600 FINEST t586 Statistics.logIt: Added: '/openbmc/linux/tools/testing/selftests/drivers/net/mlxsw/rtnetlink.sh' (ShAnalyzer) (took 79 ms)
2 2024-12-28 20:05:26.112-0600 FINER t592 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/qemu',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/qemu/chardev/spice.c'
3 2024-12-28 20:05:26.116-0600 FINEST t592 Statistics.logIt: Added: '/openbmc/qemu/chardev/spice.c' (CAnalyzer) (took 33 ms)
4 2024-1
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H A Dopengrok0.0.log1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz'
2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz'
3 2024-12-2
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