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/openbmc/linux/tools/testing/selftests/powerpc/mm/
H A Dpkey_siginfo.c1 // SPDX-License-Identifier: GPL-2.0
44 if (sinfo->si_code != SEGV_PKUERR) { in segv_handler()
50 if (sinfo->si_addr != (void *) fault_addr) { in segv_handler()
68 pgstart = (void *) ((unsigned long) fault_addr & ~(pgsize - 1)); in segv_handler()
72 * reassociate the page with the exec-only pkey since execute in segv_handler()
77 * read-write rights, change the AMR permission bits for the in segv_handler()
97 static void *protect(void *p) in protect() function
105 base = ((struct region *) p)->base; in protect()
106 size = ((struct region *) p)->size; in protect()
109 /* No read, write and execute restrictions */ in protect()
[all …]
/openbmc/linux/Documentation/misc-devices/
H A Deeprom.rst11 Addresses scanned: I2C 0x50 - 0x57
28 24C01 1K 0x50 (shadows at 0x51 - 0x57)
29 24C01A 1K 0x50 - 0x57 (Typical device on DIMMs)
30 24C02 2K 0x50 - 0x57
35 24C16 16K 0x50 (additional data at 0x51 - 0x57)
38 Atmel 34C02B 2K 0x50 - 0x57, SW write protect at 0x30-37
39 Catalyst 34FC02 2K 0x50 - 0x57, SW write protect at 0x30-37
40 Catalyst 34RC02 2K 0x50 - 0x57, SW write protect at 0x30-37
41 Fairchild 34W02 2K 0x50 - 0x57, SW write protect at 0x30-37
42 Microchip 24AA52 2K 0x50 - 0x57, SW write protect at 0x30-37
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/openbmc/u-boot/include/configs/
H A DUCP1020.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2013-2015 Arcturus Networks, Inc.
7 * Copyright 2009-2011 Freescale Semiconductor, Inc.
11 * QorIQ uCP1020-xx boards configuration file
21 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
27 #define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
52 #define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
139 #define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
187 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
188 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
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/openbmc/linux/include/soc/at91/
H A Dat91sam9_ddrsdr.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
46 #define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
53 #define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
57 #define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
58 #define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
63 #define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
64 #define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
65 #define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
74 #define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
114 #define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */
[all …]
/openbmc/linux/arch/mips/sgi-ip22/
H A Dip22-nvram.c1 // SPDX-License-Identifier: GPL-2.0
3 * ip22-nvram.c: NVRAM and serial EEPROM handling.
5 * Copyright (C) 2003 Ladislav Michl (ladis@linux-mips.org)
14 #define EEPROM_WEN 0x9800 /* write enable before prog modes */
15 #define EEPROM_WRITE 0xa000 /* serial memory write */
16 #define EEPROM_WRALL 0x8800 /* write all registers */
18 #define EEPROM_PRREAD 0xc000 /* read protect register */
19 #define EEPROM_PREN 0x9800 /* enable protect register mode */
20 #define EEPROM_PRCLEAR 0xffff /* clear protect register */
21 #define EEPROM_PRWRITE 0xa000 /* write protect register */
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/openbmc/openbmc/meta-ibm/recipes-bsp/u-boot/u-boot-aspeed-sdk/p10bmc/
H A Dibm.json52 "Write Protect: Secure Region": true,
53 "Write Protect: User region": true,
54 "Write Protect: Configure region": true,
55 "Write Protect: OTP strap region": true,
58 "Enable write Protect of OTP key retire bits": false,
69 "Extra Data Write Protection Region Size": "0x0",
110 "Enable boot SPI 3B address mode auto-clear": { "value": false },
H A Dips.json59 "Write Protect: Secure Region": true,
60 "Write Protect: User region": true,
61 "Write Protect: Configure region": true,
62 "Write Protect: OTP strap region": true,
65 "Enable write Protect of OTP key retire bits": false,
76 "Extra Data Write Protection Region Size": "0x0",
117 "Enable boot SPI 3B address mode auto-clear": { "value": false },
/openbmc/u-boot/drivers/rtc/
H A Dds1302.c2 * ds1302.c - Support for the Dallas Semiconductor DS1302 Timekeeping Chip
34 while (num--) printf("%x ", *ptr++); in DUMP()
55 unsigned char hr10:2; /* 10 (0-2) or am/pm (am/pm, 0-1) */
72 unsigned char WP:1; /* write protect 1=protect 0=unprot */
176 DPRINTF("WRITE 0x%x bytes @ 0x%x [ ", count, addr); in write_ser_drv()
179 addr&=~1; /* WRITE */ in write_ser_drv()
200 /* disable write protect */ in rtc_init()
227 bbclk.year10=100/10; /* 2000 - why not? ;) */ in rtc_init()
232 /* Write out the changes if needed */ in rtc_init()
234 /* enable write protect */ in rtc_init()
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/openbmc/u-boot/arch/arm/mach-at91/arm926ejs/
H A Deflash.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Reinhard Meyer, EMK Elektronik, reinhard.meyer@emk-elektronik.de
17 * Regions can be write/erase protected.
21 * The flash is presented to u-boot with each region being a sector,
23 * Each sector can be hardware protected (protect on/off).
27 * by u-Boot commands.
43 * do a read-modify-write for partially programmed pages
73 if ((readl(&dbu->cidr) & AT91_DBU_CID_ARCH_MASK) != AT91_DBU_CID_ARCH_9XExx) { in flash_init()
79 writel(AT91_EEFC_FCR_KEY | AT91_EEFC_FCR_FCMD_GETD, &eefc->fcr); in flash_init()
80 while ((readl(&eefc->fsr) & AT91_EEFC_FSR_FRDY) == 0) in flash_init()
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/openbmc/linux/security/
H A Dmin_addr.c1 // SPDX-License-Identifier: GPL-2.0
7 /* amount of vm to protect from userspace access by both DAC and the LSM*/
9 /* amount of vm to protect from userspace using CAP_SYS_RAWIO (DAC) */
11 /* amount of vm to protect from userspace using the LSM = CONFIG_LSM_MMAP_MIN_ADDR */
32 int mmap_min_addr_handler(struct ctl_table *table, int write, in mmap_min_addr_handler() argument
37 if (write && !capable(CAP_SYS_RAWIO)) in mmap_min_addr_handler()
38 return -EPERM; in mmap_min_addr_handler()
40 ret = proc_doulongvec_minmax(table, write, buffer, lenp, ppos); in mmap_min_addr_handler()
/openbmc/u-boot/board/freescale/common/
H A Dzm7300.c1 // SPDX-License-Identifier: GPL-2.0+
6 /* Power-One ZM7300 DPM */
91 i2c_read(I2C_DPM_ADDR, 0, -3, ret, 2); in dpm_rrp()
96 return -1; in dpm_rrp()
100 /* Write Data d into DPM register r (RAM) */
108 i2c_read(I2C_DPM_ADDR, 0, -3, ret, 1); in dpm_wrm()
113 return -1; in dpm_wrm()
117 /* Write Data d into Register r of POL(s) a */
130 i2c_read(I2C_DPM_ADDR, 0, -7, ret, 1); in dpm_wrp()
135 return -1; in dpm_wrp()
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/openbmc/u-boot/arch/x86/cpu/intel_common/
H A Dlpc.c1 // SPDX-License-Identifier: GPL-2.0
37 * lpc_early_init() - set up LPC serial ports and other early things
40 * @return 0 if OK, -ve on error
44 struct udevice *pch = dev->parent; in lpc_common_early_init()
52 count = fdtdec_get_int_array_count(gd->fdt_blob, dev_of_offset(dev), in lpc_common_early_init()
53 "intel,gen-dec", (u32 *)values, in lpc_common_early_init()
56 return -EINVAL; in lpc_common_early_init()
65 /* Write all registers but use 0 if we run out of data */ in lpc_common_early_init()
71 reg = ptr->base | PCI_COMMAND_IO | (ptr->size << 16); in lpc_common_early_init()
83 int lpc_set_spi_protect(struct udevice *dev, int bios_ctrl, bool protect) in lpc_set_spi_protect() argument
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/openbmc/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_matrix.h1 /* SPDX-License-Identifier: GPL-2.0+ */
58 u32 reserve1[16 - AT91_MATRIX_MASTERS];
60 u32 reserve2[16 - AT91_MATRIX_SLAVES];
62 u32 reserve3[32 - (2 * AT91_MATRIX_SLAVES)];
66 u32 ccr[52]; /* 0x110 - 0x1E0 Chip Configuration */
67 u32 womr; /* 0x1E4 Write Protect Mode */
68 u32 wpsr; /* 0x1E8 Write Protect Status */
100 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
102 /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
151 /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
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/openbmc/u-boot/board/synopsys/axs10x/
H A Dheaderize-axs.py12 " --header-type v1 --arc-id 0x434 --spi-flash-offset 0x0 --image u-boot.bin --elf u-boot")
15 … " --header-type v2 --arc-id 0x53 --spi-flash-offset 0x200000 --image u-boot.bin --elf u-boot")
26 # Calculate u-boot image check_sum: it is sum of all u-boot binary bytes
51 ["help", "header-type=", "arc-id=", "spi-flash-offset=", "image=", "elf="])
57 uboot_elf_filename = "u-boot"
58 uboot_bin_filename = "u-boot.bin"
59 headerised_filename = "u-boot.head"
60 uboot_scrypt_file = "u-boot-update.txt"
67 # initial header values: place where preloader will store u-boot binary,
80 if opt in ('-h', "--help"): usage(0)
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/openbmc/linux/include/linux/mtd/
H A Dspi-nor.h1 /* SPDX-License-Identifier: GPL-2.0+ */
11 #include <linux/spi/spi-mem.h>
18 * requires a 4-byte (32-bit) address.
22 #define SPINOR_OP_WRDI 0x04 /* Write disable */
23 #define SPINOR_OP_WREN 0x06 /* Write enable */
25 #define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
27 #define SPINOR_OP_WRSR2 0x3e /* Write status register 2 */
53 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
71 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
85 #define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
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/openbmc/u-boot/cmd/
H A Dotp_info.h7 #define OTP_REG_RESERVED -1
8 #define OTP_REG_VALUE -2
9 #define OTP_REG_VALID_BIT -3
74 { 22, 1, 1, "Disable dedicated BMC functions for non-BMC application" },
103 { 41, 1, 0, "Disable boot SPI 3B address mode auto-clear" },
104 { 41, 1, 1, "Enable boot SPI 3B address mode auto-clear" },
198 { 22, 1, 1, "Disable dedicated BMC functions for non-BMC application" },
232 { 41, 1, 0, "Disable boot SPI 3B address mode auto-clear" },
233 { 41, 1, 1, "Enable boot SPI 3B address mode auto-clear" },
309 { 0, 22, 1, 1, "Secure Region : Write Protect" },
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/openbmc/linux/drivers/usb/gadget/function/
H A Dg_zero.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * interfaces to its two single-configuration function drivers.
41 * Read/write access to configfs attributes is handled by configfs.
43 * This is to protect the data from concurrent access by read/write
56 * Read/write access to configfs attributes is handled by configfs.
58 * This is to protect the data from concurrent access by read/write
/openbmc/u-boot/board/freescale/p2041rdb/
H A DREADME4 with high-performance datapath acceleration architecture(DPAA), CoreNet
19 => tftp 1000000 u-boot.bin
20 => protect off all
26 => protect off all
32 => protect off all
36 5. Change DIP-switch
37 SW1[1-5] = 10110
48 SDCard which contains RCW and U-Boot image.
53 => mmc write 1000000 8 672
57 => mmc write 1000000 690 10
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/openbmc/u-boot/include/
H A Dpch.h1 /* SPDX-License-Identifier: GPL-2.0+ */
16 /* Returns HDA config info if Azalia V1CTL enabled, -ENOENT if not */
27 * struct pch_ops - Operations for the Platform Controller Hub
29 * Consider using ioctl() to add rarely used or driver-specific operations.
33 * get_spi_base() - get the address of SPI base
37 * @return 0 if OK, -ve on error (e.g. there is no SPI base)
42 * set_spi_protect() - set whether SPI flash is protected or not
45 * @protect: true to protect, false to unprotect
47 * @return 0 on success, -ENOSYS if not implemented
49 int (*set_spi_protect)(struct udevice *dev, bool protect);
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/openbmc/linux/drivers/rtc/
H A Drtc-max6900.c1 // SPDX-License-Identifier: GPL-2.0-only
21 #define MAX6900_REG_SC 0 /* seconds 00-59 */
22 #define MAX6900_REG_MN 1 /* minutes 00-59 */
23 #define MAX6900_REG_HR 2 /* hours 00-23 */
24 #define MAX6900_REG_DT 3 /* day of month 00-31 */
25 #define MAX6900_REG_MO 4 /* month 01-12 */
26 #define MAX6900_REG_DW 5 /* day of week 1-7 */
27 #define MAX6900_REG_YR 6 /* year 00-99 */
35 #define MAX6900_REG_CT_WP (1 << 7) /* Write Protect */
38 * register read/write commands
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/openbmc/linux/fs/jffs2/
H A Djffs2_fs_sb.h2 * JFFS2 -- Journalling Flash File System, Version 2.
4 * Copyright © 2001-2007 Red Hat, Inc.
5 * Copyright © 2004-2010 David Woodhouse <dwmw2@infradead.org>
39 * latter users to write to the file system if the amount if the
61 struct mutex alloc_sem; /* Used to protect all the following
62 fields, and also to protect against
63 out-of-order writing of nodes. And GC. */
81 uint8_t resv_blocks_write; /* ... allow a normal filesystem write */
96 struct jffs2_eraseblock *gcblock; /* The block we're currently garbage-collecting */
111 spinlock_t erase_completion_lock; /* Protect free_list and erasing_list
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/openbmc/u-boot/drivers/pch/
H A Dpch7.c1 // SPDX-License-Identifier: GPL-2.0+
18 /* Bits 31-14 are the base address, 13-1 are reserved, 0 is enable */ in pch7_get_spi_base()
25 static int pch7_set_spi_protect(struct udevice *dev, bool protect) in pch7_set_spi_protect() argument
29 /* Adjust the BIOS write protect to dis/allow write commands */ in pch7_set_spi_protect()
31 if (protect) in pch7_set_spi_protect()
57 return -ENODEV; in pch7_get_gpio_base()
83 .name = "intel-pch7",
/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Dmmc-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cells":
30 "#size-cells":
37 broken-cd:
42 cd-gpios:
47 non-removable:
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/openbmc/linux/Documentation/admin-guide/device-mapper/
H A Ddm-integrity.rst2 dm-integrity
5 The dm-integrity target emulates a block device that has additional
6 per-sector tags that can be used for storing integrity information.
9 writing the sector and the integrity tag must be atomic - i.e. in case of
12 To guarantee write atomicity, the dm-integrity target uses journal, it
16 The dm-integrity target can be used with the dm-crypt target - in this
17 situation the dm-crypt target creates the integrity data and passes them
18 to the dm-integrity target via bio_integrity_payload attached to the bio.
19 In this mode, the dm-crypt and dm-integrity targets provide authenticated
20 disk encryption - if the attacker modifies the encrypted device, an I/O
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/openbmc/u-boot/common/
H A Dflash.c1 // SPDX-License-Identifier: GPL-2.0+
16 /*-----------------------------------------------------------------------
20 /*-----------------------------------------------------------------------
34 if (!info || info->sector_count == 0 || info->size == 0 || to < from) { in flash_protect()
38 s_end = info->sector_count - 1; /* index of last sector */ in flash_protect()
39 b_end = info->start[0] + info->size - 1; /* bank end address */ in flash_protect()
47 * or the protect range and flash range don't overlap. in flash_protect()
49 if (info->flash_id == FLASH_UNKNOWN || in flash_protect()
50 to < info->start[0] || from > b_end) { in flash_protect()
54 for (i=0; i<info->sector_count; ++i) { in flash_protect()
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