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/openbmc/linux/drivers/clocksource/
H A Dtimer-tegra186.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2019-2020 NVIDIA Corporation. All rights reserved.
24 /* timer registers */
63 unsigned int index; member
71 unsigned int index; member
87 struct tegra186_wdt *wdt; member
95 writel_relaxed(value, tmr->regs + offset); in tmr_writel()
98 static void wdt_writel(struct tegra186_wdt *wdt, u32 value, unsigned int offset) in wdt_writel() argument
100 writel_relaxed(value, wdt->regs + offset); in wdt_writel()
103 static u32 wdt_readl(struct tegra186_wdt *wdt, unsigned int offset) in wdt_readl() argument
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/openbmc/linux/Documentation/devicetree/bindings/watchdog/
H A Dmarvell,cn10624-wdt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/marvell,cn10624-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell Global Timer (GTI) system watchdog
10 - Bharat Bhushan <bbhushan2@marvell.com>
13 - $ref: watchdog.yaml#
18 - enum:
19 - marvell,cn9670-wdt
20 - marvell,cn10624-wdt
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H A Dsamsung-wdt.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/watchdog/samsung-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC Watchdog Timer Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
14 after a preset amount of time during which the WDT reset event has not
20 - samsung,s3c2410-wdt # for S3C2410
21 - samsung,s3c6410-wdt # for S3C6410, S5PV210 and Exynos4
22 - samsung,exynos5250-wdt # for Exynos5250
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/openbmc/linux/drivers/watchdog/
H A Ds3c2410_wdt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * S3C2410 Watchdog Timer Support
15 #include <linux/timer.h>
71 * DOC: Quirk flags for different Samsung watchdog IP-cores
76 * differences in both watchdog and PMU IP-cores should be accounted for. Quirk
83 * write-only, writing any values to this register clears the interrupt, but
87 * WDT reset request. On old SoCs it's usually called MASK_WDT_RESET_REQUEST,
94 * watchdog timer reset.
97 * register. If 'mask_bit' bit is set, PMU will disable WDT reset when
135 * struct s3c2410_wdt_variant - Per-variant config data
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H A Dpc87413_wdt.c1 // SPDX-License-Identifier: GPL-2.0+
3 * NS pc87413-wdt Watchdog Timer driver for Linux 2.6.x.x
5 * This code is based on wdt.c with original copyright.
12 * This material is provided "AS-IS" and at no charge.
41 #define MODNAME "pc87413 WDT"
42 #define DPFX MODNAME " - DEBUG: "
44 #define WDT_INDEX_IO_PORT (io+0) /* I/O port base (index register) */
48 #define WDCTL 0x10 /* Watchdog-Timer-Control-Register */
55 static int swc_base_addr = -1;
58 static unsigned long timer_enabled; /* is the timer enabled? */
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H A Dmarvell_gti_wdt.c1 // SPDX-License-Identifier: GPL-2.0
30 * Driver will use hardware in mode-3 above so that system can reboot in case
79 /* wdt_timer_idx used for timer to be used for system watchdog */
90 writeq(GTI_CWD_INT_PENDING_STATUS(priv->wdt_timer_idx), in gti_wdt_interrupt()
91 priv->base + GTI_CWD_INT); in gti_wdt_interrupt()
103 priv->base + GTI_CWD_POKE(priv->wdt_timer_idx)); in gti_wdt_ping()
113 if (!wdev->pretimeout) in gti_wdt_start()
114 return -EINVAL; in gti_wdt_start()
116 set_bit(WDOG_HW_RUNNING, &wdev->status); in gti_wdt_start()
119 writeq(GTI_CWD_INT_PENDING_STATUS(priv->wdt_timer_idx), in gti_wdt_start()
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H A Dmachzwd.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MachZ ZF-Logic Watchdog Timer driver for Linux
6 * any of this software. This material is provided "AS-IS" in
15 * wd#1 - 2 seconds;
16 * wd#2 - 7.2 ms;
21 * 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com>
30 #include <linux/timer.h>
45 #define INDEX 0x218 macro
74 #define zf_writew(port, data) { outb(port, INDEX); outw(data, DATA_W); }
75 #define zf_writeb(port, data) { outb(port, INDEX); outb(data, DATA_B); }
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H A Dsbc8360.c1 // SPDX-License-Identifier: GPL-2.0+
8 * on acquirewdt.c which is based on wdt.c.
13 * is based on wdt.c.
15 * (c) Copyright 2000-2001 Marek Michalkiewicz <marekm@linux.org.pl>
17 * Based on acquirewdt.c which is based on wdt.c.
25 * "AS-IS" and at no charge.
29 * 14-Dec-2001 Matt Domsch <Matt_Domsch@dell.com>
58 * Watchdog Timer Configuration
60 * The function of the watchdog timer is to reset the system automatically
61 * and is defined at I/O port 0120H and 0121H. To enable the watchdog timer
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/openbmc/linux/drivers/hwmon/
H A Dnct7904.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * nct7904.c - driver for Nuvoton NCT7904D.
98 #define WDT_TIMER_REG 0xE3 /* R/W Watchdog Timer Register */
99 #define WDT_SOFT_EN 0x55 /* Enable soft watchdog timer */
100 #define WDT_SOFT_DIS 0xAA /* Disable soft watchdog timer */
110 /*The timeout range is 1-255 minutes*/
130 struct watchdog_device wdt; member
149 mutex_lock(&data->bank_lock); in nct7904_bank_lock()
150 if (data->bank_sel == bank) in nct7904_bank_lock()
152 ret = i2c_smbus_write_byte_data(data->client, BANK_SEL_REG, bank); in nct7904_bank_lock()
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/openbmc/u-boot/drivers/watchdog/
H A Dorion_wdt.c17 #include <wdt.h>
47 writel(priv->timeout, priv->reg + priv->wdt_counter_offset); in orion_wdt_reset()
57 priv->timeout = (u32) timeout; in orion_wdt_start()
60 reg = readl(priv->reg + TIMER_CTRL); in orion_wdt_start()
62 writel(reg, priv->reg + TIMER_CTRL); in orion_wdt_start()
65 writel(priv->timeout, priv->reg + priv->wdt_counter_offset); in orion_wdt_start()
68 reg = readl(priv->reg + TIMER_A370_STATUS); in orion_wdt_start()
70 writel(reg, priv->reg + TIMER_A370_STATUS); in orion_wdt_start()
72 /* Enable watchdog timer */ in orion_wdt_start()
73 reg = readl(priv->reg + TIMER_CTRL); in orion_wdt_start()
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/openbmc/linux/Documentation/devicetree/bindings/powerpc/fsl/
H A Dmpc5200.txt2 ----------------------------
4 (c) 2006-2009 Secret Lab Technologies Ltd
8 ------------------
9 For mpc5200 on-chip devices, the format for each compatible value is
10 <chip>-<device>[-<mode>]. The OS should be able to match a device driver
21 "fsl,mpc5200-<device>".
29 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
34 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
35 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
39 "fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to
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/openbmc/linux/drivers/media/platform/mediatek/vpu/
H A Dmtk_vpu.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Andrew-CT Chen <andrew-ct.chen@mediatek.com>
18 #include <linux/dma-mapping.h>
33 /* maximum program/data TCM (Tightly-Coupled Memory) size */
68 /* vpu inter-processor communication interrupt */
74 * enum vpu_fw_type - VPU firmware type
86 * struct vpu_mem - VPU extended program/data memory information
98 * struct vpu_regs - VPU TCM and configuration registers
100 * @tcm: the register for VPU Tightly-Coupled Memory
111 * struct vpu_wdt_handler - VPU watchdog reset handler
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/openbmc/linux/arch/arm/boot/dts/marvell/
H A Dorion5x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2012 Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
7 #address-cells = <1>;
8 #size-cells = <1>;
11 interrupt-parent = <&intc>;
18 #address-cells = <2>;
19 #size-cells = <1>;
22 devbus_bootcs: devbus-bootcs {
23 compatible = "marvell,orion-devbus";
26 #address-cells = <1>;
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H A Dkirkwood.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
3 #include <dt-bindings/gpio/gpio.h>
8 #address-cells = <1>;
9 #size-cells = <1>;
11 interrupt-parent = <&intc>;
14 #address-cells = <1>;
15 #size-cells = <0>;
22 clock-names = "cpu_clk", "ddrclk", "powersave";
33 compatible = "marvell,kirkwood-mbus", "simple-bus";
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/openbmc/qemu/include/hw/arm/
H A Dallwinner-h3.h21 * The Allwinner H3 is a System on Chip containing four ARM Cortex-A7
28 * https://linux-sunxi.org/File:Allwinner_H3_Datasheet_V1.2.pdf
32 * https://linux-sunxi.org/H3
39 #include "hw/timer/allwinner-a10-pit.h"
41 #include "hw/misc/allwinner-h3-ccu.h"
42 #include "hw/misc/allwinner-cpucfg.h"
43 #include "hw/misc/allwinner-h3-dramc.h"
44 #include "hw/misc/allwinner-h3-sysctrl.h"
45 #include "hw/misc/allwinner-sid.h"
46 #include "hw/sd/allwinner-sdhost.h"
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/openbmc/linux/arch/powerpc/boot/dts/
H A Dlite5200.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2006-2007 Secret Lab Technologies Ltd.
9 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
16 interrupt-parent = <&mpc5200_pic>;
19 #address-cells = <1>;
20 #size-cells = <0>;
25 d-cache-line-size = <32>;
26 i-cache-line-size = <32>;
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H A Dmpc8313erdb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
25 #address-cells = <1>;
26 #size-cells = <0>;
31 d-cache-line-size = <32>;
32 i-cache-line-size = <32>;
33 d-cache-size = <16384>;
34 i-cache-size = <16384>;
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H A Dmpc8315erdb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /dts-v1/;
12 #address-cells = <1>;
13 #size-cells = <1>;
26 #address-cells = <1>;
27 #size-cells = <0>;
32 d-cache-line-size = <32>;
33 i-cache-line-size = <32>;
34 d-cache-size = <16384>;
35 i-cache-size = <16384>;
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/openbmc/u-boot/arch/arm/dts/
H A Dkirkwood.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 #include <dt-bindings/input/input.h>
4 #include <dt-bindings/gpio/gpio.h>
10 interrupt-parent = <&intc>;
13 #address-cells = <1>;
14 #size-cells = <0>;
21 clock-names = "cpu_clk", "ddrclk", "powersave";
32 compatible = "marvell,kirkwood-mbus", "simple-bus";
33 #address-cells = <2>;
34 #size-cells = <1>;
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H A Dimx7s.dtsi5 * This file is dual-licensed: you can use it either under the terms
44 #include <dt-bindings/clock/imx7d-clock.h>
45 #include <dt-bindings/power/imx7-power.h>
46 #include <dt-bindings/gpio/gpio.h>
47 #include <dt-bindings/input/input.h>
48 #include <dt-bindings/interrupt-controller/arm-gic.h>
49 #include "imx7d-pinfunc.h"
52 #address-cells = <1>;
53 #size-cells = <1>;
56 * pre-existing /chosen node to be available to insert the
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7s.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
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H A Dimx27.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 #include "imx27-pinfunc.h"
7 #include <dt-bindings/clock/imx27-clock.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
17 * pre-existing /chosen node to be available to insert the
43 aitc: aitc-interrupt-controller@10040000 {
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H A Dimx25.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 #include <dt-bindings/gpio/gpio.h>
6 #include "imx25-pinfunc.h"
9 #address-cells = <1>;
10 #size-cells = <1>;
13 * pre-existing /chosen node to be available to insert the
46 #address-cells = <1>;
47 #size-cells = <0>;
50 compatible = "arm,arm926ej-s";
56 asic: asic-interrupt-controller@68000000 {
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/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8960.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
8 #include <dt-bindings/mfd/qcom-rpm.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
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H A Dqcom-mdm9615.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
13 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
14 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
15 #include <dt-bindings/mfd/qcom-rpm.h>
16 #include <dt-bindings/soc/qcom,gsbi.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
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