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/openbmc/qemu/target/xtensa/core-de233_fpu/
H A Dcore-matmap.h150 * way = each TLB (ITLB and DTLB) consists of a number of "ways"
153 * one way matches the vaddr; if none match, it is a miss;
155 * each way can be independently configured in terms of number of
161 * min-wired = a "min-wired" way can be used to map a single (minimum-sized)
163 * is non-auto-refill (some other way(s) must be auto-refill),
168 * TLB way entries are virtually indexed.
173 * whose bits n*4+3 .. n*4 index the list of page sizes for way n
174 * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
178 * this list; unsupported sizes for a given way are zero in the list;
194 #define XCHAL_ITLB_WAYS 7 /* number of ways (n-way set-associative TLB) */
[all …]
/openbmc/linux/arch/nios2/mm/
H A Dtlb.c47 unsigned int way; in replace_tlb_one_pid() local
50 /* remember pid/way until we return. */ in replace_tlb_one_pid()
55 for (way = 0; way < cpuinfo.tlb_num_ways; way++) { in replace_tlb_one_pid()
60 tlbmisc = TLBMISC_RD | (way << TLBMISC_WAY_SHIFT); in replace_tlb_one_pid()
73 (way << TLBMISC_WAY_SHIFT); in replace_tlb_one_pid()
126 unsigned int way; in flush_tlb_one() local
131 /* remember pid/way until we return. */ in flush_tlb_one()
136 for (way = 0; way < cpuinfo.tlb_num_ways; way++) { in flush_tlb_one()
140 tlbmisc = TLBMISC_RD | (way << TLBMISC_WAY_SHIFT); in flush_tlb_one()
147 pr_debug("Flush entry by writing way=%dl pid=%ld\n", in flush_tlb_one()
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/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dcore-matmap.h134 * way = each TLB (ITLB and DTLB) consists of a number of "ways"
137 * one way matches the vaddr; if none match, it is a miss;
139 * each way can be independently configured in terms of number of
145 * min-wired = a "min-wired" way can be used to map a single (minimum-sized)
147 * is non-auto-refill (some other way(s) must be auto-refill),
152 * TLB way entries are virtually indexed.
157 * whose bits n*4+3 .. n*4 index the list of page sizes for way n
158 * (XCHAL_xTLB_SETm_PAGESZ_LOG2_LIST for set m corresponding to way n);
162 * this list; unsupported sizes for a given way are zero in the list;
178 #define XCHAL_ITLB_WAYS 1 /* number of ways (n-way set-associative TLB) */
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A De300.h84 #define HID2_IWLCK_001 0x00002000 /* way 0 locked */
85 #define HID2_IWLCK_010 0x00004000 /* way 0 through way 1 locked */
86 #define HID2_IWLCK_011 0x00006000 /* way 0 through way 2 locked */
87 #define HID2_IWLCK_100 0x00008000 /* way 0 through way 3 locked */
88 #define HID2_IWLCK_101 0x0000A000 /* way 0 through way 4 locked */
89 #define HID2_IWLCK_110 0x0000C000 /* way 0 through way 5 locked */
/openbmc/linux/arch/x86/kernel/cpu/
H A Dcacheinfo.c60 { 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
61 { 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
62 { 0x09, LVL_1_INST, 32 }, /* 4-way set assoc, 64 byte line size */
63 { 0x0a, LVL_1_DATA, 8 }, /* 2 way set assoc, 32 byte line size */
64 { 0x0c, LVL_1_DATA, 16 }, /* 4-way set assoc, 32 byte line size */
65 { 0x0d, LVL_1_DATA, 16 }, /* 4-way set assoc, 64 byte line size */
66 { 0x0e, LVL_1_DATA, 24 }, /* 6-way set assoc, 64 byte line size */
67 { 0x21, LVL_2, 256 }, /* 8-way set assoc, 64 byte line size */
68 { 0x22, LVL_3, 512 }, /* 4-way set assoc, sectored cache, 64 byte line size */
69 { 0x23, LVL_3, MB(1) }, /* 8-way set assoc, sectored cache, 64 byte line size */
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/openbmc/linux/arch/sh/mm/
H A Dcache-sh2a.c26 static void sh2a_flush_oc_line(unsigned long v, int way) in sh2a_flush_oc_line() argument
28 unsigned long addr = (v & 0x000007f0) | (way << 11); in sh2a_flush_oc_line()
76 int way; in sh2a__flush_wback_region() local
77 for (way = 0; way < nr_ways; way++) { in sh2a__flush_wback_region()
79 sh2a_flush_oc_line(v, way); in sh2a__flush_wback_region()
106 int way; in sh2a__flush_purge_region() local
108 for (way = 0; way < nr_ways; way++) in sh2a__flush_purge_region()
109 sh2a_flush_oc_line(v, way); in sh2a__flush_purge_region()
H A Dcache-sh2.c28 int way; in sh2__flush_wback_region() local
29 for (way = 0; way < 4; way++) { in sh2__flush_wback_region()
30 unsigned long data = __raw_readl(addr | (way << 12)); in sh2__flush_wback_region()
33 __raw_writel(data, addr | (way << 12)); in sh2__flush_wback_region()
H A Dcache-debugfs.c29 unsigned int waysize, way; in cache_debugfs_show() local
66 for (way = 0; way < cache->ways; way++) { in cache_debugfs_show()
71 seq_printf(file, "Way %d\n", way); in cache_debugfs_show()
/openbmc/qemu/docs/
H A Dqdev-device-use.txt45 The new way keeps the parts separate: you create the host part with
57 In the new way, this becomes something like
73 * media is special. In the old way, it selects disk vs. CD-ROM with
74 if=ide, if=scsi and if=xen. The new way uses DEVNAME for that.
90 The old way implicitly creates SCSI controllers as needed. The new
91 way makes that explicit:
128 For USB devices, the old way was actually different:
134 The old way provided much less control than -drive's OPTS... The new
135 way fixes that:
156 The new way keeps the parts separate: you create the host part with
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/openbmc/linux/arch/xtensa/include/asm/
H A Dtlbflush.h130 static inline void write_dtlb_entry (pte_t entry, int way) in write_dtlb_entry() argument
133 : : "r" (way), "r" (entry) ); in write_dtlb_entry()
136 static inline void write_itlb_entry (pte_t entry, int way) in write_itlb_entry() argument
139 : : "r" (way), "r" (entry) ); in write_itlb_entry()
176 static inline unsigned long read_dtlb_virtual (int way) in read_dtlb_virtual() argument
179 __asm__ __volatile__("rdtlb0 %0, %1\n\t" : "=a" (tmp), "+a" (way)); in read_dtlb_virtual()
183 static inline unsigned long read_dtlb_translation (int way) in read_dtlb_translation() argument
186 __asm__ __volatile__("rdtlb1 %0, %1\n\t" : "=a" (tmp), "+a" (way)); in read_dtlb_translation()
190 static inline unsigned long read_itlb_virtual (int way) in read_itlb_virtual() argument
193 __asm__ __volatile__("ritlb0 %0, %1\n\t" : "=a" (tmp), "+a" (way)); in read_itlb_virtual()
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/openbmc/linux/arch/arm/mm/
H A Dcache-xsc3l2.c44 int set, way; in xsc3_l2_inv_all() local
49 for (way = 0; way < CACHE_WAY_PER_SET; way++) { in xsc3_l2_inv_all()
50 set_way = (way << 29) | (set << 5); in xsc3_l2_inv_all()
149 * optimize L2 flush all operation by set/way format
154 int set, way; in xsc3_l2_flush_all() local
159 for (way = 0; way < CACHE_WAY_PER_SET; way++) { in xsc3_l2_flush_all()
160 set_way = (way << 29) | (set << 5); in xsc3_l2_flush_all()
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dcache_v7_asm.S45 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
46 clz r5, r4 @ find bit position of way size increment
52 ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
54 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
58 mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
61 subs r4, r4, #1 @ decrement the way
115 ands r4, r4, r1, lsr #3 @ find maximum number on the way size
116 clz r5, r4 @ find bit position of way size increment
122 ARM( orr r11, r10, r4, lsl r5 ) @ factor way and cache number into r11
124 THUMB( orr r11, r10, r6 ) @ factor way and cache number into r11
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/openbmc/linux/scripts/tracing/
H A Dftrace-bisect.sh25 # The old (slow) way, for kernels before v5.1.
27 # [old-way] # cat available_filter_functions > ~/full-file
29 # [old-way] *** Note *** this process will take several minutes to update the
30 # [old-way] filters. Setting multiple functions is an O(n^2) operation, and we
31 # [old-way] are dealing with thousands of functions. So go have coffee, talk
32 # [old-way] with your coworkers, read facebook. And eventually, this operation
33 # [old-way] will end.
35 # The new way (using numbers) is an O(n) operation, and usually takes less than a second.
45 # For either the new or old way, the rest of the operations remain the same.
78 # The way to figure out if the problem function is bad, just do:
/openbmc/linux/arch/x86/crypto/
H A Dtwofish_glue_3way.c3 * Glue Code for 3-way parallel assembler optimized version of Twofish
79 .base.cra_driver_name = "ecb-twofish-3way",
91 .base.cra_driver_name = "cbc-twofish-3way",
115 * On Atom, twofish-3way is slower than original assembler in is_blacklisted_cpu()
116 * implementation. Twofish-3way trades off some performance in in is_blacklisted_cpu()
128 * On Pentium 4, twofish-3way is slower than original assembler in is_blacklisted_cpu()
147 "twofish-x86_64-3way: performance on this CPU " in twofish_3way_init()
149 "twofish-x86_64-3way.\n"); in twofish_3way_init()
166 MODULE_DESCRIPTION("Twofish Cipher Algorithm, 3-way parallel asm optimized");
/openbmc/linux/arch/openrisc/include/asm/
H A Dspr_defs.h72 #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) argument
73 #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) argument
74 #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) argument
75 #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) argument
80 #define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) argument
81 #define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100) argument
82 #define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100) argument
83 #define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100) argument
92 #define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200) argument
93 #define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200) argument
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/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm2837.dtsi57 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
60 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
72 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
75 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
87 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
90 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
102 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
105 i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
120 cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
H A Dbcm2836.dtsi58 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
61 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
72 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
75 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
86 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
89 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
100 d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
103 i-cache-sets = <512>; // 32KiB(size)/32(line-size)=1024ways/2-way set
118 cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
/openbmc/linux/arch/arc/mm/
H A Dtlb.c175 * Flush the entire MM for userland. The fastest way is to move to Next ASID
204 * -Here the fastest way (if range is too large) is to move to next ASID
688 #define SET_WAY_TO_IDX(mmu, set, way) ((set) * mmu->ways + (way)) argument
715 int is_valid, way; in do_tlb_overlap_fault() local
719 for (way = 0, is_valid = 0; way < n_ways; way++) { in do_tlb_overlap_fault()
721 SET_WAY_TO_IDX(mmu, set, way)); in do_tlb_overlap_fault()
723 pd0[way] = read_aux_reg(ARC_REG_TLBPD0); in do_tlb_overlap_fault()
724 is_valid |= pd0[way] & _PAGE_PRESENT; in do_tlb_overlap_fault()
725 pd0[way] &= PAGE_MASK; in do_tlb_overlap_fault()
733 for (way = 0; way < n_ways - 1; way++) { in do_tlb_overlap_fault()
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/openbmc/linux/Documentation/arch/x86/
H A Dentry_64.rst28 either way.
36 magically-generated functions that make their way to common_interrupt()
64 Now, there's a secondary complication: there's a cheap way to test
65 which mode the CPU is in and an expensive way.
67 The cheap way is to pick this info off the entry frame on the kernel
75 The expensive (paranoid) way is to read back the MSR_GS_BASE value
96 stack but before we executed SWAPGS, then the only safe way to check
/openbmc/linux/arch/mips/include/asm/octeon/
H A Dcvmx-l2c.h183 * Return the L2 Cache way partitioning for a given core.
199 * a way, while a 1 bit blocks the core from evicting any
200 * lines from that way. There must be at least one allowed
201 * way (0 bit) in the mask.
212 * Return the L2 Cache way partitioning for the hw blocks.
214 * Returns The mask specifying the reserved way. 0 bits in mask indicates
225 * a way, while a 1 bit blocks the core from evicting any
226 * lines from that way. There must be at least one allowed
227 * way (0 bit) in the mask.
295 * @index: Which way to read from.
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/openbmc/linux/arch/mips/kernel/
H A Dbmips_5xxx_init.S126 * Determine sets per way: IS
128 * This field contains the number of sets (i.e., indices) per way of
137 /* sets per way = (64<<IS) */
164 /* v0 now have sets per way, multiply it by line size now
174 * i) 0x0: Direct mapped, ii) 0x1: 2-way, iii) 0x2: 3-way, iv) 0x3:
175 * 4-way, v) 0x4 - 0x7: Reserved.
219 * Determine sets per way: IS
221 * This field contains the number of sets (i.e., indices) per way of
230 /* sets per way = (64<<IS) */
256 /* v0 now have sets per way, multiply it by line size now
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/openbmc/linux/arch/powerpc/mm/nohash/
H A Dtlb_low.S102 oris r7,r6,0x8000 /* specify way explicitly */
129 /* 476 variant. There's not simple way to do this, hopefully we'll
137 lis r7,0x8000 /* Specify way explicitly */
142 li r4,0 /* Current way */
144 andi. r0,r8,1 /* Check if way 0 is bolted */
145 mtctr r9 /* Load way counter */
148 2: /* For each way */
149 or r5,r3,r4 /* Make way|index for tlbre */
152 3: addis r4,r4,0x2000 /* Next way */
155 rlwimi r7,r5,0,1,2 /* Insert way number */
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/openbmc/phosphor-host-ipmid/
H A Dmeson.options135 # IPMI whitelist mechanism is not needed by everyone; offer a way to disable it
153 …description: 'The Entity Manager Decorators flag is enabled by default; offer a way to disable it',
161 description: 'Dynamic sensors stack is enabled by default; offer a way to disable it',
167 description: 'Dynamic sensors stack is enabled by default; offer a way to disable it',
173 description: 'Hybrid sensors stack is disabled by default; offer a way to enable it',
179 description: 'OEM sensor SDR parsing is disabled by default; offer a way to enable it',
187 description: 'Sensor cache stack is disabled by default; offer a way to enable it',
/openbmc/linux/arch/mips/mm/
H A Dcerr-sb1.c321 unsigned short way; in extract_ic() local
330 for (way = 0; way < 4; way++) { in extract_ic()
344 : "r" ((way << 13) | addr)); in extract_ic()
347 if (way == 0) { in extract_ic()
377 way, va, valid, taghi, taglo); in extract_ic()
399 : "r" ((way << 13) | addr | (offset << 3))); in extract_ic()
477 int valid, way; in extract_dc() local
485 for (way = 0; way < 4; way++) { in extract_dc()
498 : "r" ((way << 13) | addr)); in extract_dc()
502 if (way == 0) { in extract_dc()
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/openbmc/openbmc/poky/meta/files/common-licenses/
H A DSimple-2.021 …way, you may only recover direct damages up to the amount you paid for it (that is zero if you did…
26 …s a license form to use in any way that you find helpful. To avoid confusion, however, if you cha…

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