| /openbmc/u-boot/drivers/watchdog/ |
| H A D | Kconfig | 1 menu "Watchdog Timer Support"
3 config WATCHDOG config
4 bool "Enable U-Boot watchdog reset"
6 This option enables U-Boot watchdog support where U-Boot is using
7 watchdog_reset function to service watchdog device in U-Boot. Enable
8 this option if you want to service enabled watchdog by U-Boot. Disable
9 this option if you want U-Boot to start watchdog but never service it.
15 bool "Disable reset watchdog"
17 Disable reset watchdog, which can let WATCHDOG_RESET invalid, so
18 that the watchdog will not be fed in u-boot.
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| H A D | orion_wdt.c | 2 * drivers/watchdog/orion_wdt.c
4 * Watchdog driver for Orion/Kirkwood processors
46 /* Reload watchdog duration */ in orion_wdt_reset()
47 writel(priv->timeout, priv->reg + priv->wdt_counter_offset); in orion_wdt_reset()
57 priv->timeout = (u32) timeout; in orion_wdt_start()
59 /* Enable the fixed watchdog clock input */ in orion_wdt_start()
60 reg = readl(priv->reg + TIMER_CTRL); in orion_wdt_start()
62 writel(reg, priv->reg + TIMER_CTRL); in orion_wdt_start()
64 /* Set watchdog duration */ in orion_wdt_start()
65 writel(priv->timeout, priv->reg + priv->wdt_counter_offset); in orion_wdt_start()
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| /openbmc/linux/Documentation/ABI/stable/ |
| H A D | sysfs-driver-firmware-zynqmp | 1 What: /sys/devices/platform/firmware\:zynqmp-firmware/ggs*
11 The register is reset during system or power-on
17 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
18 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
22 # cat /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
23 # echo 0x1234ABCD > /sys/devices/platform/firmware\:zynqmp-firmware/ggs0
27 What: /sys/devices/platform/firmware\:zynqmp-firmware/pggs*
38 This register is only reset by the power-on reset
46 # cat /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
47 # echo <value> > /sys/devices/platform/firmware\:zynqmp-firmware/pggs0
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| /openbmc/phosphor-watchdog/src/ |
| H A D | watchdog.hpp | 7 #include <xyz/openbmc_project/State/Watchdog/server.hpp>
17 namespace watchdog namespace
22 using WatchdogInherits = sdbusplus::server::object_t<Base::Watchdog>;
24 /** @class Watchdog
25 * @brief OpenBMC watchdog implementation.
27 * xyz.openbmc_project.State.Watchdog DBus API.
29 class Watchdog : public WatchdogInherits class
32 Watchdog() = delete;
33 ~Watchdog() = default;
34 Watchdog(const Watchdog&) = delete;
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| /openbmc/phosphor-watchdog/test/ |
| H A D | watchdog.cpp | 1 #include "watchdog.hpp"
15 namespace watchdog namespace
23 // Test Watchdog functionality
35 wdog(std::make_unique<Watchdog>( in WdogTest()
36 bus, TEST_PATH, event, Watchdog::ActionTargetMap(), std::nullopt, in WdogTest()
42 wdog->interval(milliseconds(defaultInterval).count()); in WdogTest()
43 // Initially the watchdog would be disabled in WdogTest()
44 EXPECT_FALSE(wdog->enabled()); in WdogTest()
53 // Watchdog object
54 std::unique_ptr<Watchdog> wdog;
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| /openbmc/linux/drivers/watchdog/ |
| H A D | smsc37b787_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * SMsC 37B787 Watchdog Timer driver for Linux 2.6.x.x
9 * any of this software. This material is provided "AS-IS" in
12 * (C) Copyright 2003-2006 Sven Anders <anders@anduras.de>
15 * 2003 - Created version 1.0 for Linux 2.4.x.
16 * 2006 - Ported to Linux 2.6, added nowayout and MAGICCLOSE
21 * A Watchdog Timer (WDT) is a hardware circuit that can
26 * via the /dev/watchdog special device file that userspace is
28 * occurs, the driver will usually tell the hardware watchdog
29 * that everything is in order, and that the watchdog should wait
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| H A D | starfive-wdt.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Starfive Watchdog driver
15 #include <linux/watchdog.h>
17 /* JH7100 Watchdog register define */
31 /* JH7110 Watchdog register define */
35 * [0]: reset enable;
36 * [1]: interrupt enable && watchdog enable
56 #define STARFIVE_WDT_JH7100_INTCLR_AVA_SHIFT 1 /* Watchdog can clear interrupt when 0 */
74 MODULE_PARM_DESC(heartbeat, "Watchdog heartbeat in seconds. (default="
77 "Watchdog is started at boot time if set to 1, default="
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| H A D | pc87413_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * NS pc87413-wdt Watchdog Timer driver for Linux 2.6.x.x
12 * This material is provided "AS-IS" and at no charge.
22 #include <linux/watchdog.h>
42 #define DPFX MODNAME " - DEBUG: "
48 #define WDCTL 0x10 /* Watchdog-Timer-Control-Register */
49 #define WDTO 0x11 /* Watchdog timeout register */
50 #define WDCFG 0x12 /* Watchdog config register */
55 static int swc_base_addr = -1;
66 /* -- Low level function ----------------------------------------*/
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| H A D | sa1100_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Watchdog driver for the SA11x0/PXA2xx
10 * "AS-IS" and at no charge.
27 #include <linux/watchdog.h>
40 #define REG_OWER 0x0018 /* OS timer Watch-dog Enable Reg. */
41 #define REG_OIER 0x001C /* OS timer Interrupt Enable Reg. */
48 #define OWER_WME (1 << 0) /* Watchdog Match Enable */
50 #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
51 #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
52 #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
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| H A D | at91sam9_wdt.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * drivers/watchdog/at91sam9_wdt.h
9 * Watchdog Timer (WDT) - System peripherals regsters.
20 #define AT91_WDT_CR 0x00 /* Watchdog Control Register */
24 #define AT91_WDT_MR 0x04 /* Watchdog Mode Register */
29 #define AT91_WDT_WDFIEN BIT(12) /* Fault Interrupt Enable */
30 #define AT91_SAM9X60_WDDIS BIT(12) /* Watchdog Disable */
33 #define AT91_WDT_WDDIS BIT(15) /* Watchdog Disable */
39 #define AT91_WDT_SR 0x08 /* Watchdog Status Register */
40 #define AT91_WDT_WDUNF BIT(0) /* Watchdog Underflow */
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
4 # Watchdog device configuration
7 menuconfig WATCHDOG config
8 bool "Watchdog Timer Support"
11 character special file /dev/watchdog with major number 10 and minor
12 number 130 using mknod ("man mknod"), you will get a watchdog, i.e.:
16 on-line as fast as possible after a lock-up. There's both a watchdog
18 reboot the machine) and a driver for hardware watchdog boards, which
21 <file:Documentation/watchdog/watchdog-api.rst> in the kernel source.
23 The watchdog is usually used together with the watchdog daemon
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| H A D | via_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * VIA Chipset Watchdog Driver
10 * Caveat: PnP must be enabled in BIOS to allow full access to watchdog
11 * control registers. If not, the watchdog must be configured in BIOS manually.
22 #include <linux/watchdog.h>
26 #define VIA_WDT_CONF 0xec /* watchdog enable state */
29 #define VIA_WDT_CONF_ENABLE 0x01 /* 1: enable watchdog */
30 #define VIA_WDT_CONF_MMIO 0x02 /* 1: enable watchdog MMIO */
33 * The MMIO region contains the watchdog control register and the
42 #define VIA_WDT_FIRED 0x02 /* 1: restarted by expired watchdog */
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| H A D | cadence_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence WDT driver - Used by Xilinx Zynq
5 * Copyright (C) 2010 - 2014 Xilinx, Inc.
18 #include <linux/watchdog.h>
21 /* Supports 1 - 516 sec */
54 "Watchdog time in seconds. (default="
59 "Watchdog cannot be stopped once started (default="
63 * struct cdns_wdt - Watchdog device structure
70 * @cdns_wdt_device: watchdog device structure
72 * Structure containing parameters specific to cadence watchdog.
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| H A D | imx2_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Watchdog driver for IMX2 and later processors
11 * NOTE: MX1 has a slightly different Watchdog than MX2 and later:
14 * ---- -----
15 * Registers: 32-bit 16-bit
17 * Need to enable clk: No Yes
32 #include <linux/watchdog.h>
34 #define DRIVER_NAME "imx2-wdt"
37 #define IMX2_WDT_WCR_WT (0xFF << 8) /* -> Watchdog Timeout Field */
38 #define IMX2_WDT_WCR_WDW BIT(7) /* -> Watchdog disable for WAIT */
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| H A D | rn5t618_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Watchdog driver for Ricoh RN5T618 PMIC
12 #include <linux/watchdog.h>
14 #define DRIVER_NAME "rn5t618-wdt"
20 MODULE_PARM_DESC(timeout, "Initial watchdog timeout in seconds");
23 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
33 * watchdog expiration times. If the watchdog is not accessed before
59 return -EINVAL; in rn5t618_wdt_set_timeout()
61 ret = regmap_update_bits(wdt->rn5t618->regmap, RN5T618_WATCHDOG, in rn5t618_wdt_set_timeout()
65 wdt_dev->timeout = rn5t618_wdt_map[i].time; in rn5t618_wdt_set_timeout()
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| H A D | i6300esb.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * i6300esb: Watchdog timer driver for Intel 6300ESB chipset
8 * based on i810-tco.c which is in turn based on softdog.c
12 * 6300ESB chip : document number 300641-004
21 * Change driver to use the watchdog subsystem
35 #include <linux/watchdog.h>
49 #define ESB_TIMER1_REG(w) ((w)->base + 0x00)/* Timer1 value after each reset */
50 #define ESB_TIMER2_REG(w) ((w)->base + 0x04)/* Timer2 value after each reset */
51 #define ESB_GINTSR_REG(w) ((w)->base + 0x08)/* General Interrupt Status Reg */
52 #define ESB_RELOAD_REG(w) ((w)->base + 0x0c)/* Reload register */
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| H A D | ftwdt010_wdt.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Watchdog driver for Faraday Technology FTWDT010
7 * Inspired by the out-of-tree drivers from OpenWRT:
20 #include <linux/watchdog.h>
54 u32 enable; in ftwdt010_enable() local
56 writel(timeout * WDT_CLOCK, gwdt->base + FTWDT010_WDLOAD); in ftwdt010_enable()
57 writel(WDRESTART_MAGIC, gwdt->base + FTWDT010_WDRESTART); in ftwdt010_enable()
59 enable = WDCR_CLOCK_5MHZ | WDCR_SYS_RST; in ftwdt010_enable()
60 writel(enable, gwdt->base + FTWDT010_WDCR); in ftwdt010_enable()
62 enable |= WDCR_WDINTR; in ftwdt010_enable()
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| /openbmc/linux/Documentation/devicetree/bindings/mfd/ |
| H A D | rohm,bd9576-pmic.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mfd/rohm,bd9576-pmic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matti Vaittinen <mazziesaccount@gmail.com>
14 powering the R-Car series processors.
16 monitoring. A watchdog logic with slow ping/windowed modes is also included.
21 - rohm,bd9576
22 - rohm,bd9573
32 rohm,vout1-en-low:
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| /openbmc/openbmc/meta-phosphor/recipes-phosphor/watchdog/ |
| H A D | phosphor-watchdog_git.bb | 1 SUMMARY = "Phosphor Watchdog application"
2 DESCRIPTION = "Application that implements software watchdog"
3 HOMEPAGE = "http://github.com/openbmc/phosphor-watchdog"
6 LICENSE = "Apache-2.0"
10 inherit obmc-phosphor-dbus-service
15 DEPENDS += "phosphor-dbus-interfaces"
16 DEPENDS += "phosphor-logging"
19 SRC_URI = "git://github.com/openbmc/phosphor-watchdog;branch=master;protocol=https"
24 -Dtests=disabled \
27 # Copies config file having arguments for host watchdog
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| /openbmc/u-boot/arch/m68k/cpu/mcf52x2/ |
| H A D | cpu.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
11 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
17 #include <watchdog.h>
33 out_8(&rcm->rcr, RCM_RCR_SOFTRST); in do_reset()
46 strmhz(buf1, gd->cpu_clk), in print_cpuinfo()
47 strmhz(buf2, gd->bus_clk)); in print_cpuinfo()
58 out_be16(&wdt->sr, 0x5555); in watchdog_reset()
59 out_be16(&wdt->sr, 0xaaaa); in watchdog_reset()
66 /* reset watchdog counter */ in watchdog_disable()
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| /openbmc/linux/Documentation/devicetree/bindings/watchdog/ |
| H A D | atmel,sama5d4-wdt.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/watchdog/atmel,sama5d4-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Atmel SAMA5D4 Watchdog Timer (WDT) Controller
10 - Eugen Hristev <eugen.hristev@microchip.com>
13 - $ref: watchdog.yaml#
18 - atmel,sama5d4-wdt
19 - microchip,sam9x60-wdt
20 - microchip,sama7g5-wdt
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| H A D | xlnx,xps-timebase-wdt.yaml | 1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/watchdog/xlnx,xps-timebase-wdt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx AXI/PLB softcore and window Watchdog Timer
10 - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11 - Srinivas Neeli <srinivas.neeli@amd.com>
14 The Timebase watchdog timer(WDT) is a free-running 32 bit counter.
15 WDT uses a dual-expiration architecture. After one expiration of
22 - $ref: watchdog.yaml#
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| /openbmc/docs/ |
| H A D | host-management.md | 3 This document describes the host-management interfaces of the OpenBMC object
9 [REST-cheatsheet](https://github.com/openbmc/docs/blob/master/REST-cheatsheet.md#establish-rest-con…
15 …-k -H "Content-Type: application/json" -X POST https://${bmc}/login -d '{"username" : "root", "pa…
16 $ curl -k -H "X-Auth-Token: $token" https://${bmc}/xyz/openbmc_project/...
26 items and are not necessarily FRUs (field-replaceable units). If the system
35 - `Version`: A code version associated with this item.
36 - `Present`: Indicates whether this item is present in the system (True/False).
37 - `Functional`: Indicates whether this item is functioning in the system
44 $ curl -k -H "X-Auth-Token: $token" https://${bmc}/xyz/openbmc_project/inventory/enumerate
48 …$ curl -k -H "X-Auth-Token: $token" https://${bmc}/xyz/openbmc_project/inventory/system/chassis/mo…
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| /openbmc/u-boot/arch/arm/mach-socfpga/ |
| H A D | misc.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
14 #include <watchdog.h>
44 return -EINVAL; in dram_init()
63 clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); in v7_outer_cache_enable()
65 writel(0x0, &pl310->pl310_tag_latency_ctrl); in v7_outer_cache_enable()
66 writel(0x10, &pl310->pl310_data_latency_ctrl); in v7_outer_cache_enable()
68 /* enable BRESP, instruction and data prefetch, full line of zeroes */ in v7_outer_cache_enable()
69 setbits_le32(&pl310->pl310_aux_ctrl, in v7_outer_cache_enable()
74 /* Enable the L2 cache */ in v7_outer_cache_enable()
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| /openbmc/qemu/include/hw/watchdog/ |
| H A D | wdt_imx2.h | 4 * i.MX2 Watchdog IP block
9 * See the COPYING file in the top-level directory.
35 #define IMX2_WDT_WCR_WT (0xFF << 8) /* Watchdog Timeout Field */
40 #define IMX2_WDT_WCR_WDE BIT(2) /* Watchdog Enable */
41 #define IMX2_WDT_WCR_WDBG BIT(1) /* Watchdog Debug Enable */
42 #define IMX2_WDT_WCR_WDZST BIT(0) /* Watchdog Timer Suspend */
56 #define IMX2_WDT_WICR_WIE BIT(15) /* Interrupt Enable */
64 #define IMX2_WDT_WMCR_PDE BIT(0) /* Power-Down Enable */
|