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/openbmc/openbmc-test-automation/gui/gui_test/operations_menu/
H A Dtest_reboot_bmc_sub_menu.robot3 Documentation Test OpenBMC GUI "Reboot BMC" sub-menu of "Operation" menu.
50 # Delay added for cancel button to appear.
54 Wait Until Element Is Not Visible ${xpath_reboot_cancel_button} timeout=15
63 # Delay added for confirm button to appear.
68 Wait Until Keyword Succeeds 1 min 5 sec Is BMC Unpingable
69 Wait For Host To Ping ${OPENBMC_HOST} 1 min
71 Wait Until Keyword Succeeds 3 min 10 sec Is BMC Operational
73 Wait Until Element Is Visible ${xpath_reboot_bmc_button} timeout=10
88 # Delay added for confirm button to appear.
106 # Delay added for confirm button to appear.
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H A Dtest_server_power_operations_sub_menu.robot3 Documentation Test OpenBMC GUI "Server power operations" sub-menu of "Operations".
17 ${xpath_enable_onetime_boot_checkbox} //*[contains(@class,'custom-checkbox')]
18 ${xpath_boot_option_select} //*[@id='boot-option']
19 ${xpath_shutdown_button} //*[@data-test-id='serverPowerOperations-button-shutDown…
20 ${xpath_reboot_button} //*[@data-test-id='serverPowerOperations-button-reboot']
21 ${xpath_poweron_button} //*[@data-test-id='serverPowerOperations-button-powerOn']
23 ${xpath_shutdown_orderly_radio} //*[@data-test-id='serverPowerOperations-radio-shutdownO…
24 ${xpath_shutdown_immediate_radio} //*[@data-test-id='serverPowerOperations-radio-shutdownI…
26 ${xpath_current_power_state} //*[@data-test-id='powerServerOps-text-hostStatus']
27 ${xpath_reboot_immediate_radio} //*[@data-test-id='serverPowerOperations-radio-rebootImm…
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/openbmc/phosphor-fan-presence/monitor/
H A Dpower_off_action.hpp27 * there is a delay before the power off.
30 * the D-Bus call to do the power off, so it can be mocked
48 * @param[in] name - The action name. Used for tracing.
49 * @param[in] powerInterface - The object used to invoke the power off.
50 * @param[in] powerOffFunc - A function to call right before the power
80 * @param[in] force - If the cancel should be forced
82 * @return bool - If the cancel was allowed/successful
89 * @return const std::string& - The name
147 * and will execute a hard power off after some delay.
162 * @param[in] delay - The amount of time in seconds to wait before
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/openbmc/openbmc/meta-security/recipes-core/initrdscripts/initramfs-framework-dm/
H A Ddmverity13 . /usr/share/misc/dm-verity.env
16 delay=${bootparam_rootdelay:-1}
17 timeout=${bootparam_roottimeout:-5}
20 if [ "${SEPARATE_HASH}" -eq "1" ]; then
21 while [ ! -b "/dev/disk/by-partuuid/${ROOT_UUID}" ]; do
22 if [ $(( $C * $delay )) -gt $timeout ]; then
26 debug "Sleeping for $delay second(s) to wait for root data to settle..."
27 sleep $delay
32 --data-block-size=${DATA_BLOCK_SIZE} \
34 /dev/disk/by-partuuid/${ROOT_UUID} \
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/openbmc/u-boot/drivers/usb/host/
H A Dehci-omap.c1 // SPDX-License-Identifier: GPL-2.0+
4 * (C) Copyright 2004-2008
20 #include <asm/ehci-omap.h>
33 rev = readl(&uhh->rev); in omap_uhh_reset()
36 writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc); in omap_uhh_reset()
40 /* Wait for soft RESET to complete */ in omap_uhh_reset()
41 while (!(readl(&uhh->syss) & 0x1)) { in omap_uhh_reset()
44 return -1; in omap_uhh_reset()
50 /* Set No-Idle, No-Standby */ in omap_uhh_reset()
51 writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc); in omap_uhh_reset()
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/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_write_leveling.c1 // SPDX-License-Identifier: GPL-2.0
59 * Args: freq - current sequence frequency
60 * dram_info - main struct
66 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
70 /* Debug message - Start Read leveling procedure */ in ddr3_write_leveling_hw()
71 DEBUG_WL_S("DDR3 - Write Leveling - Starting HW WL procedure\n"); in ddr3_write_leveling_hw()
86 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw()
87 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_write_leveling_hw()
93 /* Wait */ in ddr3_write_leveling_hw()
97 } while (reg); /* Wait for '0' */ in ddr3_write_leveling_hw()
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H A Dddr3_read_leveling.c1 // SPDX-License-Identifier: GPL-2.0
56 * Args: dram_info - main struct
57 * freq - current sequence frequency
65 /* Debug message - Start Read leveling procedure */ in ddr3_read_leveling_hw()
66 DEBUG_RL_S("DDR3 - Read Leveling - Starting HW RL procedure\n"); in ddr3_read_leveling_hw()
74 reg |= (dram_info->cs_ena << REG_DRAM_TRAINING_CS_OFFS); in ddr3_read_leveling_hw()
76 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_read_leveling_hw()
82 /* Wait */ in ddr3_read_leveling_hw()
86 } while (reg); /* Wait for '0' */ in ddr3_read_leveling_hw()
91 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
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/openbmc/qemu/tests/qemu-iotests/
H A D14844 [inject-error]
53 driveopts = ['driver=quorum', 'vote-threshold=2']
54 driveopts.append('read-pattern=%s' % self.read_pattern)
56 iotests.qemu_img('create', '-f', iotests.imgfmt, imgs[i], '1M')
62 driveopts.append('children.%d.node-name=img%d' % (i, i))
78 for event in self.vm.get_qmp_events(wait=True):
80 self.assert_qmp(event, 'data/node-name', node)
81 self.assert_qmp(event, 'data/sector-num', sector)
91 delay = 10
95 self.vm.qtest("clock_step %d" % delay)
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/openbmc/qemu/hw/sh4/
H A Dsh7750_regs.h2 * SH-7750 memory-mapped registers
6 * Document Number ADE-602-124C, Rev. 4.0, 4/21/00, Hitachi Ltd.
8 * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
42 * All register has 2 addresses: in 0xff000000 - 0xffffffff (P4 address) and
43 * in 0x1f000000 - 0x1fffffff (area 7 address)
55 /* Page Table Entry High register - PTEH */
64 /* Page Table Entry Low register - PTEL */
70 #define SH7750_PTEL_V 0x00000100 /* Validity (0-entry is invalid) */
73 #define SH7750_PTEL_SZ_1KB 0x00000000 /* 1-kbyte page */
74 #define SH7750_PTEL_SZ_4KB 0x00000010 /* 4-kbyte page */
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/openbmc/u-boot/board/creative/xfi3/
H A Dxfi3.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Creative ZEN X-Fi3 board
16 #include <asm/arch/iomux-mx23.h>
17 #include <asm/arch/imx-regs.h>
68 /* Phison SD-NAND bridge */ in board_mmc_init()
81 if (mxs_wait_mask_clr(&regs->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, in mxsfb_write_byte()
83 return -ETIMEDOUT; in mxsfb_write_byte()
87 &regs->hw_lcdif_transfer_count); in mxsfb_write_byte()
90 &regs->hw_lcdif_ctrl_clr); in mxsfb_write_byte()
93 writel(LCDIF_CTRL_DATA_SELECT, &regs->hw_lcdif_ctrl_set); in mxsfb_write_byte()
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/openbmc/u-boot/drivers/spi/
H A Dmscc_bb_spi.c1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
16 #include <linux/delay.h>
28 /* Delay 24 instructions for this particular application */
33 if (!priv->cs_active) { in mscc_bb_spi_cs_activate()
37 priv->cs_num = cs; in mscc_bb_spi_cs_activate()
41 priv->clk1 = ICPU_SW_MODE_SW_SPI_SCK; in mscc_bb_spi_cs_activate()
42 priv->clk2 = 0; in mscc_bb_spi_cs_activate()
45 priv->clk1 = 0; in mscc_bb_spi_cs_activate()
46 priv->clk2 = ICPU_SW_MODE_SW_SPI_SCK; in mscc_bb_spi_cs_activate()
50 priv->svalue = (ICPU_SW_MODE_SW_PIN_CTRL_MODE | /* Bitbang */ in mscc_bb_spi_cs_activate()
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H A Dtegra_spi.h1 /* SPDX-License-Identifier: GPL-2.0+ */
8 int frequency; /* Default clock frequency, -1 for none */
10 uint deactivate_delay_us; /* Delay to wait after deactivate */
H A Dzynq_spi.c1 // SPDX-License-Identifier: GPL-2.0+
58 uint deactivate_delay_us; /* Delay to wait after deactivate */
59 uint activate_delay_us; /* Delay to wait after activate */
74 struct zynq_spi_platdata *plat = bus->platdata; in zynq_spi_ofdata_to_platdata()
75 const void *blob = gd->fdt_blob; in zynq_spi_ofdata_to_platdata()
78 plat->regs = (struct zynq_spi_regs *)devfdt_get_addr(bus); in zynq_spi_ofdata_to_platdata()
81 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", in zynq_spi_ofdata_to_platdata()
83 plat->deactivate_delay_us = fdtdec_get_int(blob, node, in zynq_spi_ofdata_to_platdata()
84 "spi-deactivate-delay", 0); in zynq_spi_ofdata_to_platdata()
85 plat->activate_delay_us = fdtdec_get_int(blob, node, in zynq_spi_ofdata_to_platdata()
[all …]
H A Drk_spi.c1 // SPDX-License-Identifier: GPL-2.0+
7 * (C) Copyright 2008-2013 Rockchip Electronics
14 #include <dt-structs.h>
31 s32 frequency; /* Default clock frequency, -1 for none */
33 uint deactivate_delay_us; /* Delay to wait after deactivate */
34 uint activate_delay_us; /* Delay to wait after activate */
55 debug("ctrl0: \t\t0x%08x\n", readl(&regs->ctrlr0)); in rkspi_dump_regs()
56 debug("ctrl1: \t\t0x%08x\n", readl(&regs->ctrlr1)); in rkspi_dump_regs()
57 debug("ssienr: \t\t0x%08x\n", readl(&regs->enr)); in rkspi_dump_regs()
58 debug("ser: \t\t0x%08x\n", readl(&regs->ser)); in rkspi_dump_regs()
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/openbmc/openbmc/poky/meta/recipes-core/initrdscripts/initramfs-framework/
H A Drootfs10 if [ -z "$ROOTFS_DIR" ]; then
14 delay=${bootparam_rootdelay:-1}
15 timeout=${bootparam_roottimeout:-5}
16 while ! mountpoint -q $ROOTFS_DIR; do
17 if [ $(( $C * $delay )) -gt $timeout ]; then
21 if [ -n "$bootparam_root" ]; then
24 if [ "`echo ${bootparam_root} | cut -c1-5`" = "UUID=" ]; then
25 root_uuid=`echo $bootparam_root | cut -c6-`
26 bootparam_root="/dev/disk/by-uuid/$root_uuid"
27 elif [ "`echo ${bootparam_root} | cut -c1-9`" = "PARTUUID=" ]; then
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/openbmc/u-boot/arch/arm/dts/
H A Dexynos5250-spring.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/input/input.h>
48 samsung,bl1-offset = <0x1400>;
49 samsung,bl2-offset = <0x3400>;
50 u-boot-memory = "/memory";
51 u-boot-offset = <0x3e00000 0x100000>;
56 #address-cells = <1>;
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/openbmc/u-boot/cmd/aspeed/
H A Dplltest.c9 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <clk-uclass.h>
30 #include <dt-bindings/clock/ast2600-clock.h>
33 #include <dt-bindings/clock/ast2600-clock.h>
37 /* ------------------------------------------------------------------------- */
65 ulCounter = (pll_rate/1000) * 512 / 25000 - 1; in cal_ast2600_28nm_pll_rate()
66 ulLowLimit = ulCounter * (100 - ulErrRate) / 100; in cal_ast2600_28nm_pll_rate()
73 //2. Wait until SCU320[29:16] = 0 in cal_ast2600_28nm_pll_rate()
77 } while ((ulData & 0x3fff0000) && (i++<1000)); //wait until SCU320[29:16]=0 in cal_ast2600_28nm_pll_rate()
86 //4. Delay 1ms in cal_ast2600_28nm_pll_rate()
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/openbmc/openbmc-test-automation/ipmi/
H A Dtest_ipmi_user.robot76 # Delay added for IPMI user to get enabled.
84 ${index}= Evaluate ${random_userid} - 1
145 # Delay added for user password to get set.
197 # Delay added for IPMI user to get enable
301 # Delay added for user privilege to get set.
305 Wait And Confirm New Username And Password ${random_username} ${valid_password}
347 ... Wait Until Keyword Succeeds 15 sec 5 sec
354 # Delay added for user password to get set.
358 Wait Until Keyword Succeeds 15 sec 5 sec Verify IPMI Username And Password
380 # Delay added for user privileges to get set.
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/openbmc/qemu/include/qemu/
H A Dratelimit.h10 * See the COPYING.LIB file in the top-level directory.
29 /** Calculate and return delay for next request in ns
33 * in the current time slice, return 0 (i.e. no delay). Otherwise
45 QEMU_LOCK_GUARD(&limit->lock); in ratelimit_calculate_delay()
46 if (!limit->slice_quota) { in ratelimit_calculate_delay()
50 assert(limit->slice_ns); in ratelimit_calculate_delay()
52 if (limit->slice_end_time < now) { in ratelimit_calculate_delay()
55 limit->slice_start_time = now; in ratelimit_calculate_delay()
56 limit->slice_end_time = now + limit->slice_ns; in ratelimit_calculate_delay()
57 limit->dispatched = 0; in ratelimit_calculate_delay()
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/openbmc/u-boot/doc/device-tree-bindings/video/
H A Dexynos-fb.txt5 compatible: should be "samsung,exynos-fimd"
9 samsung,vl-col: X resolution of the panel
10 samsung,vl-row: Y resolution of the panel
11 samsung,vl-freq: Refresh rate
12 samsung,vl-bpix: Bits per pixel
13 samsung,vl-hspw: Hsync value
14 samsung,vl-hfpd: Right margin
15 samsung,vl-hbpd: Left margin
16 samsung,vl-vspw: Vsync value
17 samsung,vl-vfpd: Lower margin
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/openbmc/openbmc/poky/meta/recipes-sato/matchbox-keyboard/files/
H A D80matchboxkeyboard.sh8 CMD="matchbox-keyboard -d"
10 if [ "$HAVE_KEYBOARD_PORTRAIT" = "1" -a "$HAVE_KEYBOARD_LANDSCAPE" = "0" ]; then
11 CMD="matchbox-keyboard -d -o landscape"
12 elif [ "$HAVE_KEYBOARD_LANDSCAPE" = "1" -a "$HAVE_KEYBOARD_PORTRAIT" = "0" ]; then
13 CMD="matchbox-keyboard -d -o portrait"
18 # Delay to make sure the window manager is active
20 dbus-wait org.matchbox_project.desktop Loaded && $CMD &
/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Software/
H A DActivationBlocksTransition.interface.yaml7 A typical use of this would be to prevent (delay) the power-on of a managed
9 transitions, might start the power-on sequence and then wait for any object
12 update is currently being performed and the power-on sequence may safely
/openbmc/openbmc-test-automation/gui/gui_test/hardware_status_menu/
H A Dtest_sensors_sub_menu.robot3 Documentation Test OpenBMC GUI "Sensors" sub-menu.
15 ${xpath_sensors_search} //input[contains(@class,"search-input")]
16 ${xpath_filter_ok} //*[@data-test-id='tableFilter-checkbox-OK']
17 ${xpath_filter_warning} //*[@data-test-id='tableFilter-checkbox-Warning']
18 ${xpath_filter_critical} //*[@data-test-id='tableFilter-checkbox-Critical']
19 ${xpath_filter_clear_all} //*[@data-test-id='tableFilter-button-clearAll']
20 ${xpath_selected_severity} //*[@class="d-inline-block mb-0"]
55 Wait Until Page Contains Element ${xpath_sensors_search}
57 Wait Until Page Contains Ambient timeout=120s
64 Wait Until Page Contains Element ${xpath_sensors_filter} timeout=15s
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/openbmc/u-boot/board/sandisk/sansa_fuze_plus/
H A Dsfp.c1 // SPDX-License-Identifier: GPL-2.0+
16 #include <asm/arch/iomux-mx23.h>
17 #include <asm/arch/imx-regs.h>
219 if (mxs_wait_mask_clr(&regs->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN, in mxsfb_write_byte()
221 return -ETIMEDOUT; in mxsfb_write_byte()
225 &regs->hw_lcdif_transfer_count); in mxsfb_write_byte()
228 &regs->hw_lcdif_ctrl_clr); in mxsfb_write_byte()
231 writel(LCDIF_CTRL_DATA_SELECT, &regs->hw_lcdif_ctrl_set); in mxsfb_write_byte()
233 writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set); in mxsfb_write_byte()
235 if (mxs_wait_mask_clr(&regs->hw_lcdif_lcdif_stat_reg, 1 << 29, in mxsfb_write_byte()
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/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun4i.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c
8 * and earlier U-Boot Allwinner A10 SPL work
10 * (C) Copyright 2007-2012
38 * Wait up to 1s for mask to be clear in given reg.
46 * Wait up to 1s for mask to be set in given reg.
68 writel(0, &timer->cpu_cfg); in mctl_ddr3_reset()
69 reg_val = readl(&timer->cpu_cfg); in mctl_ddr3_reset()
73 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
75 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
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