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/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dmtd.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
19 User-defined MTD device name. Can be used to assign user friendly
24 '#address-cells':
27 '#size-cells':
34 - compatible
37 "@[0-9a-f]+$":
[all …]
H A Dnand-macronix.txt2 -----------------------------------
4 Macronix NANDs support randomizer operation for scrambling user data,
11 For more high-reliability concern, if subpage write is not available
17 - randomizer enable: should be "mxic,enable-randomizer-otp"
21 nand: nand-controller@unit-address {
25 mxic,enable-randomizer-otp;
/openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/User/
H A DTOTPAuthenticator.interface.yaml2 This interface defines methods and properties required for Time-based
3 One-time Password (TOTP) multi-factor authentication at user level to
4 support multi-factor authentication secret key setup for each user. This
5 interface implemented by each user object to support TOTP based
9 - name: CreateSecretKey
11 This method setup Time-based One-time Password (TOTP) authenticator
12 secret key for the given user and returns secret key string to share
13 secret key to user.
15 - name: SecretKey
18 Secret key string which will be shared to user to setup TOTP
[all …]
/openbmc/u-boot/cmd/
H A Dotp_info.h7 #define OTP_REG_RESERVED -1
8 #define OTP_REG_VALUE -2
9 #define OTP_REG_VALID_BIT -3
74 { 22, 1, 1, "Disable dedicated BMC functions for non-BMC application" },
103 { 41, 1, 0, "Disable boot SPI 3B address mode auto-clear" },
104 { 41, 1, 1, "Enable boot SPI 3B address mode auto-clear" },
198 { 22, 1, 1, "Disable dedicated BMC functions for non-BMC application" },
232 { 41, 1, 0, "Disable boot SPI 3B address mode auto-clear" },
233 { 41, 1, 1, "Enable boot SPI 3B address mode auto-clear" },
285 { 0, 3, 1, 0, "User region ECC disable" },
[all …]
/openbmc/linux/drivers/mtd/spi-nor/
H A Dotp.c1 // SPDX-License-Identifier: GPL-2.0
3 * OTP support for SPI NOR flashes
10 #include <linux/mtd/spi-nor.h>
14 #define spi_nor_otp_region_len(nor) ((nor)->params->otp.org->len)
15 #define spi_nor_otp_n_regions(nor) ((nor)->params->otp.org->n_regions)
18 * spi_nor_otp_read_secr() - read security register
27 * an one-time-programmable memory area, consisting of multiple bytes (usually
28 * 256). Thus one "security register" maps to one OTP region.
34 * Return: number of bytes read successfully, -errno otherwise
43 read_opcode = nor->read_opcode; in spi_nor_otp_read_secr()
[all …]
/openbmc/u-boot/include/mtd/
H A Dmtd-abi.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org> et al.
45 * @MTD_OPS_RAW: data are transferred as-is, with no error correction;
59 * struct mtd_write_req - data structure for requesting a write operation
64 * @usr_data: user-provided data buffer
65 * @usr_oob: user-provided OOB buffer
70 * writes in various modes. To write to OOB-only, set @usr_data == NULL, and to
71 * write data-only, set @usr_oob == NULL. However, setting both @usr_data and
111 /* OTP mode selection */
150 /* Write out-of-band data from MTD */
[all …]
/openbmc/linux/include/uapi/mtd/
H A Dmtd-abi.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
3 * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org> et al.
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
55 * @MTD_OPS_RAW: data are transferred as-is, with no error correction;
69 * struct mtd_write_req - data structure for requesting a write operation
74 * @usr_data: user-provided data buffer
75 * @usr_oob: user-provided OOB buffer
80 * writes in various modes. To write to OOB-only, set @usr_data == NULL, and to
81 * write data-only, set @usr_oob == NULL. However, setting both @usr_data and
95 * struct mtd_read_req_ecc_stats - ECC statistics for a read operation
[all …]
/openbmc/openbmc/meta-ibm/recipes-bsp/u-boot/u-boot-aspeed-sdk/p10bmc/
H A Dibm.json39 "Disable OTP Memory BIST Mode": true,
41 "User region ECC enable": true,
53 "Write Protect: User region": true,
55 "Write Protect: OTP strap region": true,
58 "Enable write Protect of OTP key retire bits": false,
60 "OTP memory lock enable": false,
72 "User define data: random number low": "0x0",
73 "User define data: random number high": "0x0",
110 "Enable boot SPI 3B address mode auto-clear": { "value": false },
H A Dips.json46 "Disable OTP Memory BIST Mode": true,
48 "User region ECC enable": true,
60 "Write Protect: User region": true,
62 "Write Protect: OTP strap region": true,
65 "Enable write Protect of OTP key retire bits": false,
67 "OTP memory lock enable": false,
79 "User define data: random number low": "0x0",
80 "User define data: random number high": "0x0",
117 "Enable boot SPI 3B address mode auto-clear": { "value": false },
/openbmc/linux/Documentation/devicetree/bindings/nvmem/
H A Dmicrochip,lan9662-otpc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/microchip,lan9662-otpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip LAN9662 OTP Controller (OTPC)
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 OTP controller drives a NVMEM memory where system specific data
15 user specific data could be stored.
18 - $ref: nvmem.yaml#
23 - items:
[all …]
H A Dmicrochip,sama7g5-otpc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/microchip,sama7g5-otpc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip SAMA7G5 OTP Controller (OTPC)
10 - Claudiu Beznea <claudiu.beznea@microchip.com>
13 OTP controller drives a NVMEM memory where system specific data
15 settings, chip identifiers) or user specific data could be stored.
18 - $ref: nvmem.yaml#
23 - const: microchip,sama7g5-otpc
[all …]
/openbmc/openbmc/meta-arm/meta-arm-bsp/documentation/corstone1000/
H A Dsoftware-architecture.rst2 # Copyright (c) 2022-2024, Arm Limited.
4 # SPDX-License-Identifier: MIT
12 Arm Corstone-1000
15 Arm Corstone-1000 is a reference solution for IoT devices. It is part of
19 Corstone-1000 software plus hardware reference solution is PSA Level-2 ready
21 More information on the Corstone-1000 subsystem product and design can be
23 `Arm Corstone-1000 Software`_ and `Arm Corstone-1000 Technical Overview`_.
28 present in the user-guide document.
34 The software architecture of Corstone-1000 platform is a reference
49 cryptographic functions. It is based on an Cortex-M0+ processor,
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/openbmc/linux/Documentation/devicetree/bindings/nvmem/layouts/
H A Dkontron,sl28-vpd.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/layouts/kontron,sl28-vpd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVMEM layout of the Kontron SMARC-sAL28 vital product data
10 - Michael Walle <michael@walle.cc>
15 on-board ethernet devices are derived from this base MAC address by
22 const: kontron,sl28-vpd
24 serial-number:
30 base-mac-address:
[all …]
H A Donie,tlv-layout.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/layouts/onie,tlv-layout.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
14 infrastructure shall provide a non-volatile memory with a table whose the
26 const: onie,tlv-layout
28 product-name:
32 part-number:
36 serial-number:
[all …]
/openbmc/linux/drivers/mtd/chips/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 support any device that is CFI-compliant, you need to enable this
18 tristate "Detect non-CFI AMD/JEDEC-compatible flash chips"
22 This option enables JEDEC-style probing of flash chips which are not
24 CFI-targeted flash drivers for any chips which are identified which
26 covers most AMD/Fujitsu-compatible chips and also non-CFI
53 are expected to be wired to the CPU in 'host-endian' form.
85 bool "Support 8-bit buswidth" if MTD_CFI_GEOMETRY
92 bool "Support 16-bit buswidth" if MTD_CFI_GEOMETRY
99 bool "Support 32-bit buswidth" if MTD_CFI_GEOMETRY
[all …]
/openbmc/linux/drivers/mtd/nand/onenand/
H A Donenand_base.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright © 2005-2009 Samsung Electronics
9 * Adrian Hunter <ext-adrian.hunter@nokia.com>:
10 * auto-placement support, read-while load support, various fixes
13 * Flex-OneNAND support
15 * OTP support
39 /* Default Flex-OneNAND boundary and lock respectively */
40 static int flex_bdry[MAX_DIES * 2] = { -1, 0, -1, 0 };
43 MODULE_PARM_DESC(flex_bdry, "SLC Boundary information for Flex-OneNAND"
47 " : 0->Set boundary in unlocked status"
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-connectivity/krb5/
H A Dkrb5_1.21.3.bb3 Kerberos is a trusted third-party service. That means that there is a \
19 inherit autotools-brokensep binconfig perlnative systemd update-rc.d pkgconfig
23 file://debian-suppress-usr-lib-in-krb5-config.patch;striplevel=2 \
25 file://etc/init.d/krb5-kdc \
26 file://etc/init.d/krb5-admin-server \
27 file://etc/default/krb5-kdc \
28 file://etc/default/krb5-admin-server \
29 file://krb5-kdc.service \
30 file://krb5-admin-server.service \
31 file://CVE-2024-26458_CVE-2024-26461.patch;striplevel=2 \
[all …]
/openbmc/linux/drivers/nvmem/
H A Dmicrochip-otpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * OTP Memory controller
13 #include <linux/nvmem-provider.h>
28 #define MCHP_OTPC_NAME "mchp-otpc"
32 * struct mchp_otpc - OTPC private data structure
35 * @packets: list of packets in OTP memory
36 * @npackets: number of packets in OTP memory
46 * struct mchp_otpc_packet - OTPC packet data structure
49 * @offset: packet offset (in words) in OTP memory
62 if (id >= otpc->npackets) in mchp_otpc_id_to_packet()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Drenesas,5p35023.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
14 is designed for low-power, consumer, and high-performance PCI
19 An internal OTP memory allows the user to store the configuration
20 in the device. After power up, the user can change the device register
29 …renesas.com/us/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3…
34 - renesas,5p35023
39 '#clock-cells':
[all …]
/openbmc/qemu/docs/system/riscv/
H A Dsifive_u.rst4 SiFive HiFive Unleashed Development Board is the ultimate RISC-V development
5 board featuring the Freedom U540 multi-core RISC-V processor.
8 -----------------
15 * Platform-Level Interrupt Controller (PLIC)
17 * L2 Loosely Integrated Memory (L2-LIM)
22 * 1 One-Time Programmable (OTP) memory with stored serial number
30 1 E51 core and 4 U54 core combination and the RISC-V core boots in 64-bit mode.
32 is also possible to create a 32-bit variant with the same peripherals except
33 that the RISC-V cores are replaced by the 32-bit ones (E31 and U34), to help
34 testing of 32-bit guest software.
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-ls1028a-kontron-sl28.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * Device Tree file for the Kontron SMARC-sAL28 board.
9 /dts-v1/;
10 #include "fsl-ls1028a.dtsi"
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
16 model = "Kontron SMARC-sAL28";
33 compatible = "gpio-keys";
35 power-button {
[all …]
/openbmc/linux/drivers/mtd/
H A Dmtdcore.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright © 1999-2010 David Woodhouse <dwmw2@infradead.org>
24 #include <linux/backing-dev.h>
31 #include <linux/nvmem-provider.h>
94 dev_t index = MTD_DEVT(mtd->index); in mtd_release()
96 idr_remove(&mtd_idr, mtd->index); in mtd_release()
111 debugfs_remove_recursive(mtd->dbg.dfs_dir); in mtd_device_release()
114 nvmem_unregister(mtd->nvmem); in mtd_device_release()
116 device_unregister(&mtd->dev); in mtd_device_release()
119 * Clear dev so mtd can be safely re-registered later if desired. in mtd_device_release()
[all …]
/openbmc/linux/drivers/iio/gyro/
H A Dmpu3050-core.c1 // SPDX-License-Identifier: GPL-2.0-only
39 * Register map: anything suffixed *_H is a big-endian high byte and always
76 /* Bits 8-11 select memory bank */
163 * Fullscale precision is (for finest precision) +/- 250 deg/s, so the full
184 if (mpu3050->lpf == MPU3050_DLPF_CFG_256HZ_NOLPF2) in mpu3050_get_freq()
188 freq /= (mpu3050->divisor + 1); in mpu3050_get_freq()
200 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, in mpu3050_start_sampling()
205 /* Turn on the Z-axis PLL */ in mpu3050_start_sampling()
206 ret = regmap_update_bits(mpu3050->map, MPU3050_PWR_MGM, in mpu3050_start_sampling()
214 raw_val[i] = cpu_to_be16(mpu3050->calibration[i]); in mpu3050_start_sampling()
[all …]
/openbmc/linux/drivers/mtd/devices/
H A Dmtd_dataflash.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Copyright (C) 2003-2005 SAN People (Pty) Ltd
28 * Sometimes DataFlash is packaged in MMC-format cards, although the
57 #define OP_MWRITE_BUFFER1 0x88 /* sector must be pre-erased */
58 #define OP_MWRITE_BUFFER2 0x89 /* sector must be pre-erased */
60 /* write to buffer, then write-erase to flash */
68 /* read flash to buffer, then write-erase to flash */
73 * serial number and OTP bits; and per-sector writeprotect.
129 * This usually takes 5-20 msec or so; more for sector erase.
138 dev_dbg(&spi->dev, "status %d?\n", status); in dataflash_waitready()
[all …]
/openbmc/openbmc/poky/meta/recipes-connectivity/wpa-supplicant/wpa-supplicant/
H A Dwpa_supplicant.conf10 # readable only by root user on multiuser systems.
48 # run as non-root users. However, since the control interface can be used to
51 # want to allow non-root users to use the control interface, add a new group
69 # library/default.asp?url=/library/en-us/secauthz/security/
72 # DACL (which will reject all connections). See README-Windows.txt for more
78 # wpa_supplicant is implemented based on IEEE Std 802.1X-2004 which defines
95 # non-WPA drivers when using IEEE 802.1X mode; do not try to associate with
107 # EAP fast re-authentication
108 # By default, fast re-authentication is enabled for all EAP methods that
109 # support it. This variable can be used to disable fast re-authentication.
[all …]

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