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/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dpmc.h12 uint pmc_cntrl; /* _CNTRL_0, offset 00 */
13 uint pmc_sec_disable; /* _SEC_DISABLE_0, offset 04 */
14 uint pmc_pmc_swrst; /* _PMC_SWRST_0, offset 08 */
15 uint pmc_wake_mask; /* _WAKE_MASK_0, offset 0C */
16 uint pmc_wake_lvl; /* _WAKE_LVL_0, offset 10 */
17 uint pmc_wake_status; /* _WAKE_STATUS_0, offset 14 */
18 uint pmc_sw_wake_status; /* _SW_WAKE_STATUS_0, offset 18 */
19 uint pmc_dpd_pads_oride; /* _DPD_PADS_ORIDE_0, offset 1C */
20 uint pmc_dpd_sample; /* _DPD_PADS_SAMPLE_0, offset 20 */
21 uint pmc_dpd_enable; /* _DPD_PADS_ENABLE_0, offset 24 */
[all …]
H A Ddc.h15 uint gen_incr_syncpt; /* _CMD_GENERAL_INCR_SYNCPT_0 */
16 uint gen_incr_syncpt_ctrl; /* _CMD_GENERAL_INCR_SYNCPT_CNTRL_0 */
17 uint gen_incr_syncpt_err; /* _CMD_GENERAL_INCR_SYNCPT_ERROR_0 */
19 uint reserved0[5]; /* reserved_0[5] */
22 uint win_a_incr_syncpt; /* _CMD_WIN_A_INCR_SYNCPT_0 */
23 uint win_a_incr_syncpt_ctrl; /* _CMD_WIN_A_INCR_SYNCPT_CNTRL_0 */
24 uint win_a_incr_syncpt_err; /* _CMD_WIN_A_INCR_SYNCPT_ERROR_0 */
26 uint reserved1[5]; /* reserved_1[5] */
29 uint win_b_incr_syncpt; /* _CMD_WIN_B_INCR_SYNCPT_0 */
30 uint win_b_incr_syncpt_ctrl; /* _CMD_WIN_B_INCR_SYNCPT_CNTRL_0 */
[all …]
H A Dusb.h13 uint id;
14 uint reserved0;
15 uint host;
16 uint device;
19 uint txbuf;
20 uint rxbuf;
21 uint reserved1[2];
24 uint reserved2[56];
29 uint hcs_params;
30 uint hcc_params;
[all …]
H A Dclk_rst.h12 uint pll_base; /* the control register */
14 uint pll_out[2];
15 uint pll_misc; /* other misc things */
20 uint pll_base; /* the control register */
21 uint pll_misc; /* other misc things */
25 uint pllm_base; /* the control register */
26 uint pllm_out; /* output control */
27 uint pllm_misc1; /* misc1 */
28 uint pllm_misc2; /* misc2 */
33 uint set;
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dimmap_86xx.h21 uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */
23 uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */
25 uint altcar; /* 0x10 - Alternate Configuration Attribute Register */
27 uint bptr; /* 0x20 - Boot Page Translation Register */
29 uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */
31 uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */
33 uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */
35 uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */
37 uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */
39 uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */
[all …]
H A Dimmap_8xx.h18 uint sc_siumcr;
19 uint sc_sypcr;
20 uint sc_swt;
23 uint sc_sipend;
24 uint sc_simask;
25 uint sc_siel;
26 uint sc_sivec;
27 uint sc_tesr;
29 uint sc_sdcr;
36 uint pcmc_pbr0;
[all …]
H A Dcpm_85xx.h21 #define CPM_CR_RST ((uint)0x80000000)
22 #define CPM_CR_PAGE ((uint)0x7c000000)
23 #define CPM_CR_SBLOCK ((uint)0x03e00000)
24 #define CPM_CR_FLG ((uint)0x00010000)
25 #define CPM_CR_MCN ((uint)0x00003fc0)
26 #define CPM_CR_OPCODE ((uint)0x0000000f)
78 #define CPM_DATAONLY_BASE ((uint)128)
79 #define CPM_DP_NOSPACE ((uint)0x7FFFFFFF)
81 #define CPM_FCC_SPECIAL_BASE ((uint)0x00009000)
82 #define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
[all …]
H A Dcpm_8xx.h63 #define BD_IIC_START ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
75 uint cbd_bufaddr; /* Buffer address in host memory */
95 #define PROFF_SCC1 ((uint)0x0000)
96 #define PROFF_IIC ((uint)0x0080)
97 #define PROFF_REVNUM ((uint)0x00b0)
98 #define PROFF_SCC2 ((uint)0x0100)
99 #define PROFF_SPI ((uint)0x0180)
100 #define PROFF_SCC3 ((uint)0x0200)
101 #define PROFF_SMC1 ((uint)0x0280)
102 #define PROFF_SCC4 ((uint)0x0300)
[all …]
/openbmc/linux/arch/powerpc/include/asm/
H A D8xx_immap.h19 uint sc_siumcr;
20 uint sc_sypcr;
21 uint sc_swt;
24 uint sc_sipend;
25 uint sc_simask;
26 uint sc_siel;
27 uint sc_sivec;
28 uint sc_tesr;
30 uint sc_sdcr;
37 uint pcmc_pbr0;
[all …]
H A Dcpm1.h57 extern void cpm_setbrg(uint brg, uint rate);
65 #define PROFF_SCC1 ((uint)0x0000)
66 #define PROFF_IIC ((uint)0x0080)
67 #define PROFF_SCC2 ((uint)0x0100)
68 #define PROFF_SPI ((uint)0x0180)
69 #define PROFF_SCC3 ((uint)0x0200)
70 #define PROFF_SMC1 ((uint)0x0280)
71 #define PROFF_DSP1 ((uint)0x02c0)
72 #define PROFF_SCC4 ((uint)0x0300)
73 #define PROFF_SMC2 ((uint)0x0380)
[all …]
H A Dcpm2.h20 #define CPM_CR_RST ((uint)0x80000000)
21 #define CPM_CR_PAGE ((uint)0x7c000000)
22 #define CPM_CR_SBLOCK ((uint)0x03e00000)
23 #define CPM_CR_FLG ((uint)0x00010000)
24 #define CPM_CR_MCN ((uint)0x00003fc0)
25 #define CPM_CR_OPCODE ((uint)0x0000000f)
98 #define CPM_BRG_RST ((uint)0x00020000)
99 #define CPM_BRG_EN ((uint)0x00010000)
100 #define CPM_BRG_EXTC_INT ((uint)0x00000000)
101 #define CPM_BRG_EXTC_CLK3_9 ((uint)0x00004000)
[all …]
/openbmc/u-boot/include/
H A Dlcdvideo.h11 #define LCCR_BNUM ((uint)0xfffe0000)
12 #define LCCR_EIEN ((uint)0x00010000)
13 #define LCCR_IEN ((uint)0x00008000)
14 #define LCCR_IRQL ((uint)0x00007000)
15 #define LCCR_CLKP ((uint)0x00000800)
16 #define LCCR_OEP ((uint)0x00000400)
17 #define LCCR_HSP ((uint)0x00000200)
18 #define LCCR_VSP ((uint)0x00000100)
19 #define LCCR_DP ((uint)0x00000080)
20 #define LCCR_BPIX ((uint)0x00000060)
[all …]
H A Dbitfield.h41 /* Produces a mask of set bits covering a range of a uint value */
42 static inline uint bitfield_mask(uint shift, uint width) in bitfield_mask()
48 static inline uint bitfield_extract(uint reg_val, uint shift, uint width) in bitfield_extract()
55 * Returns the newly modified uint value with the replaced field.
57 static inline uint bitfield_replace(uint reg_val, uint shift, uint width, in bitfield_replace()
58 uint bitfield_val) in bitfield_replace()
60 uint mask = bitfield_mask(shift, width); in bitfield_replace()
66 static inline uint bitfield_shift(uint mask) in bitfield_shift()
72 static inline uint bitfield_extract_by_mask(uint reg_val, uint mask) in bitfield_extract_by_mask()
74 uint shift = bitfield_shift(mask); in bitfield_extract_by_mask()
[all …]
/openbmc/linux/drivers/staging/rtl8712/
H A Drtl871x_ioctl_rtl.h21 uint oid_rt_get_signal_quality_hdl(
23 uint oid_rt_get_small_packet_crc_hdl(
25 uint oid_rt_get_middle_packet_crc_hdl(
27 uint oid_rt_get_large_packet_crc_hdl(
29 uint oid_rt_get_tx_retry_hdl(
31 uint oid_rt_get_rx_retry_hdl(
33 uint oid_rt_get_rx_total_packet_hdl(
35 uint oid_rt_get_tx_beacon_ok_hdl(
37 uint oid_rt_get_tx_beacon_err_hdl(
39 uint oid_rt_get_rx_icv_err_hdl(
[all …]
H A Drtl871x_mp_ioctl.h37 uint offset;
38 uint width;
44 uint offset;
55 uint offset;
56 uint len;
75 uint oid_rt_pro_read_register_hdl(struct oid_par_priv *poid_par_priv);
76 uint oid_rt_pro_write_register_hdl(struct oid_par_priv *poid_par_priv);
78 uint oid_rt_pro_set_data_rate_hdl(
80 uint oid_rt_pro_start_test_hdl(struct oid_par_priv *poid_par_priv);
81 uint oid_rt_pro_stop_test_hdl(struct oid_par_priv *poid_par_priv);
[all …]
H A Drtl871x_ioctl_rtl.c31 uint oid_rt_get_signal_quality_hdl(struct oid_par_priv *poid_par_priv) in oid_rt_get_signal_quality_hdl()
38 uint oid_rt_get_small_packet_crc_hdl(struct oid_par_priv *poid_par_priv) in oid_rt_get_small_packet_crc_hdl()
54 uint oid_rt_get_middle_packet_crc_hdl(struct oid_par_priv *poid_par_priv) in oid_rt_get_middle_packet_crc_hdl()
70 uint oid_rt_get_large_packet_crc_hdl(struct oid_par_priv *poid_par_priv) in oid_rt_get_large_packet_crc_hdl()
86 uint oid_rt_get_tx_retry_hdl(struct oid_par_priv *poid_par_priv) in oid_rt_get_tx_retry_hdl()
93 uint oid_rt_get_rx_retry_hdl(struct oid_par_priv *poid_par_priv) in oid_rt_get_rx_retry_hdl()
101 uint oid_rt_get_rx_total_packet_hdl(struct oid_par_priv *poid_par_priv) in oid_rt_get_rx_total_packet_hdl()
118 uint oid_rt_get_tx_beacon_ok_hdl(struct oid_par_priv *poid_par_priv) in oid_rt_get_tx_beacon_ok_hdl()
125 uint oid_rt_get_tx_beacon_err_hdl(struct oid_par_priv *poid_par_priv) in oid_rt_get_tx_beacon_err_hdl()
132 uint oid_rt_get_rx_icv_err_hdl(struct oid_par_priv *poid_par_priv) in oid_rt_get_rx_icv_err_hdl()
[all …]
/openbmc/qemu/gdb-xml/
H A Dhexagon-core.xml19 …<reg name="r00" altname="r0" bitsize="32" offset="0" encoding="uint" format="hex" group="Thread …
20 …<reg name="r01" altname="r1" bitsize="32" offset="4" encoding="uint" format="hex" group="Thread …
21 …<reg name="r02" altname="r2" bitsize="32" offset="8" encoding="uint" format="hex" group="Thread …
22 …<reg name="r03" altname="r3" bitsize="32" offset="12" encoding="uint" format="hex" group="Thread …
23 …<reg name="r04" altname="r4" bitsize="32" offset="16" encoding="uint" format="hex" group="Thread …
24 …<reg name="r05" altname="r5" bitsize="32" offset="20" encoding="uint" format="hex" group="Thread …
25 …<reg name="r06" altname="r6" bitsize="32" offset="24" encoding="uint" format="hex" group="Thread …
26 …<reg name="r07" altname="r7" bitsize="32" offset="28" encoding="uint" format="hex" group="Thread …
27 …<reg name="r08" altname="r8" bitsize="32" offset="32" encoding="uint" format="hex" group="Thread …
28 …<reg name="r09" altname="r9" bitsize="32" offset="36" encoding="uint" format="hex" group="Thread …
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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/tipcutils/tipcutils/
H A D0002-replace-non-standard-uint-with-unsigned-int.patch4 Subject: [PATCH 2/2] replace non-standard uint with unsigned int
26 -static uint client_id;
35 -static void master_to_client(uint cmd, uint msglen, uint msgcnt, uint bounce)
40 @@ -93,7 +93,7 @@ static void master_to_client(uint cmd, uint msglen, uint msgcnt, uint bounce)
44 -static void client_from_master(uint *cmd, uint *msglen, uint *msgcnt, uint *bounce)
53 -static void client_to_master(uint cmd)
58 @@ -125,7 +125,7 @@ static void client_to_master(uint cmd)
62 -static void master_from_client(uint *cmd)
67 @@ -137,7 +137,7 @@ static void master_from_client(uint *cmd)
71 -static void master_to_srv(uint cmd, uint msglen, uint msgcnt, uint echo)
[all …]
/openbmc/u-boot/arch/m68k/include/asm/
H A Dimmap_5272.h34 uint sc_mbar;
37 uint sc_pmr;
40 uint sc_dir;
46 uint int_icr1;
47 uint int_icr2;
48 uint int_icr3;
49 uint int_icr4;
50 uint int_isr;
51 uint int_pitr;
52 uint int_piwr;
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra210/
H A Dgpio.h21 uint gpio_config[TEGRA_GPIO_PORTS];
22 uint gpio_dir_out[TEGRA_GPIO_PORTS];
23 uint gpio_out[TEGRA_GPIO_PORTS];
24 uint gpio_in[TEGRA_GPIO_PORTS];
25 uint gpio_int_status[TEGRA_GPIO_PORTS];
26 uint gpio_int_enable[TEGRA_GPIO_PORTS];
27 uint gpio_int_level[TEGRA_GPIO_PORTS];
28 uint gpio_int_clear[TEGRA_GPIO_PORTS];
29 uint gpio_masked_config[TEGRA_GPIO_PORTS];
30 uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra30/
H A Dgpio.h20 uint gpio_config[TEGRA_GPIO_PORTS];
21 uint gpio_dir_out[TEGRA_GPIO_PORTS];
22 uint gpio_out[TEGRA_GPIO_PORTS];
23 uint gpio_in[TEGRA_GPIO_PORTS];
24 uint gpio_int_status[TEGRA_GPIO_PORTS];
25 uint gpio_int_enable[TEGRA_GPIO_PORTS];
26 uint gpio_int_level[TEGRA_GPIO_PORTS];
27 uint gpio_int_clear[TEGRA_GPIO_PORTS];
28 uint gpio_masked_config[TEGRA_GPIO_PORTS];
29 uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra124/
H A Dgpio.h21 uint gpio_config[TEGRA_GPIO_PORTS];
22 uint gpio_dir_out[TEGRA_GPIO_PORTS];
23 uint gpio_out[TEGRA_GPIO_PORTS];
24 uint gpio_in[TEGRA_GPIO_PORTS];
25 uint gpio_int_status[TEGRA_GPIO_PORTS];
26 uint gpio_int_enable[TEGRA_GPIO_PORTS];
27 uint gpio_int_level[TEGRA_GPIO_PORTS];
28 uint gpio_int_clear[TEGRA_GPIO_PORTS];
29 uint gpio_masked_config[TEGRA_GPIO_PORTS];
30 uint gpio_masked_dir_out[TEGRA_GPIO_PORTS];
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dcommproc.c34 #define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
63 uint
64 m8560_cpm_dpalloc(uint size, uint align) in m8560_cpm_dpalloc()
67 uint retloc; in m8560_cpm_dpalloc()
68 uint align_mask, off; in m8560_cpm_dpalloc()
69 uint savebase; in m8560_cpm_dpalloc()
97 uint
98 m8560_cpm_hostalloc(uint size, uint align) in m8560_cpm_hostalloc()
121 m8560_cpm_setbrg(uint brg, uint rate) in m8560_cpm_setbrg()
124 volatile uint *bp; in m8560_cpm_setbrg()
[all …]
/openbmc/linux/arch/powerpc/platforms/8xx/
H A Dmpc885ads.h22 #define BCSR1_ETHEN ((uint)0x20000000)
23 #define BCSR1_IRDAEN ((uint)0x10000000)
24 #define BCSR1_RS232EN_1 ((uint)0x01000000)
25 #define BCSR1_PCCEN ((uint)0x00800000)
26 #define BCSR1_PCCVCC0 ((uint)0x00400000)
27 #define BCSR1_PCCVPP0 ((uint)0x00200000)
28 #define BCSR1_PCCVPP1 ((uint)0x00100000)
30 #define BCSR1_RS232EN_2 ((uint)0x00040000)
31 #define BCSR1_PCCVCC1 ((uint)0x00010000)
34 #define BCSR4_ETH10_RST ((uint)0x80000000) /* 10Base-T PHY reset*/
[all …]
H A Dmpc86xads.h20 #define BCSR1_ETHEN ((uint)0x20000000)
21 #define BCSR1_IRDAEN ((uint)0x10000000)
22 #define BCSR1_RS232EN_1 ((uint)0x01000000)
23 #define BCSR1_PCCEN ((uint)0x00800000)
24 #define BCSR1_PCCVCC0 ((uint)0x00400000)
25 #define BCSR1_PCCVPP0 ((uint)0x00200000)
26 #define BCSR1_PCCVPP1 ((uint)0x00100000)
28 #define BCSR1_RS232EN_2 ((uint)0x00040000)
29 #define BCSR1_PCCVCC1 ((uint)0x00010000)
32 #define BCSR4_ETH10_RST ((uint)0x80000000) /* 10Base-T PHY reset*/
[all …]

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