Lines Matching full:uint
12 uint pll_base; /* the control register */
14 uint pll_out[2];
15 uint pll_misc; /* other misc things */
20 uint pll_base; /* the control register */
21 uint pll_misc; /* other misc things */
25 uint pllm_base; /* the control register */
26 uint pllm_out; /* output control */
27 uint pllm_misc1; /* misc1 */
28 uint pllm_misc2; /* misc2 */
33 uint set;
34 uint clr;
55 uint crc_rst_src; /* _RST_SOURCE_0,0x00 */
56 uint crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */
57 uint crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */
58 uint crc_reserved0; /* reserved_0, 0x1C */
59 uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */
60 uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */
61 uint crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */
62 uint crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */
63 uint crc_clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */
64 uint crc_prog_dly_clk; /* _PROG_DLY_CLK_0, 0x34 */
65 uint crc_aud_sync_clk_rate; /* _AUDIO_SYNC_CLK_RATE_0,0x38 */
66 uint crc_reserved1; /* reserved_1, 0x3C */
67 uint crc_cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,0x40 */
68 uint crc_clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */
69 uint crc_misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */
70 uint crc_clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4C */
71 uint crc_osc_ctrl; /* _OSC_CTRL_0, 0x50 */
72 uint crc_pll_lfsr; /* _PLL_LFSR_0, 0x54 */
73 uint crc_osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */
74 uint crc_osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C */
75 uint crc_reserved2[8]; /* reserved_2[8], 0x60-7C */
82 uint crc_reserved10; /* _reserved_10, 0xF8 */
83 uint crc_reserved11; /* _reserved_11, 0xFC */
85 uint crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */
87 uint crc_reserved20[32]; /* _reserved_20, 0x200-27c */
89 uint crc_clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */
90 uint crc_clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */
91 uint crc_clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */
93 uint crc_rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */
94 uint crc_rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */
95 uint crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */
97 uint crc_clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */
98 uint crc_clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29c */
99 uint crc_clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2a0 */
101 uint crc_rst_devices_y; /* _RST_DEVICES_Y_0, 0x2a4 */
102 uint crc_rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2a8 */
103 uint crc_rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2ac */
105 uint crc_reserved21[17]; /* _reserved_21, 0x2b0-2f0 */
107 uint crc_dfll_base; /* _DFLL_BASE_0, 0x2f4 */
109 uint crc_reserved22[2]; /* _reserved_22, 0x2f8-2fc */
114 uint crc_reserved30[2]; /* _reserved_30, 0x318, 0x31c */
119 uint crc_reserved31[2]; /* _reserved_31, 0x338, 0x33c */
121 uint crc_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */
122 uint crc_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */
125 uint crc_clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */
126 uint crc_clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */
128 uint crc_reserved32[2]; /* _reserved_32, 0x350,0x354 */
130 uint crc_rst_dev_vw[TEGRA_CLK_REGS_VW]; /* _RST_DEVICES_V/W_0 */
131 uint crc_clk_out_enb_vw[TEGRA_CLK_REGS_VW]; /* _CLK_OUT_ENB_V/W_0 */
132 uint crc_cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */
133 uint crc_super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36C */
134 uint crc_cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */
135 uint crc_super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */
136 uint crc_clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */
137 uint crc_clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */
138 uint crc_cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */
139 uint crc_cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */
140 uint crc_cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */
141 uint crc_reserved33[9]; /* _reserved_33, 0x38c-3ac */
142 uint crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* 0x3B0-0x42C */
148 uint crc_rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */
149 uint crc_rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */
150 uint crc_rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */
151 uint crc_rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR_0, 0x45C */
152 uint crc_clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET_0, 0x460 */
153 uint crc_clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR_0, 0x464 */
154 uint crc_clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET_0, 0x468 */
155 uint crc_clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR_0, 0x46C */
156 uint crc_cpu_cmplx_status; /* _CPU_CMPLX_STATUS_0, 0x470 */
157 uint crc_reserved40[1]; /* _reserved_40, 0x474 */
158 uint crc_intstatus; /* __INTSTATUS_0, 0x478 */
159 uint crc_intmask; /* __INTMASK_0, 0x47C */
160 uint crc_utmip_pll_cfg0; /* _UTMIP_PLL_CFG0_0, 0x480 */
161 uint crc_utmip_pll_cfg1; /* _UTMIP_PLL_CFG1_0, 0x484 */
162 uint crc_utmip_pll_cfg2; /* _UTMIP_PLL_CFG2_0, 0x488 */
164 uint crc_plle_aux; /* _PLLE_AUX_0, 0x48C */
165 uint crc_sata_pll_cfg0; /* _SATA_PLL_CFG0_0, 0x490 */
166 uint crc_sata_pll_cfg1; /* _SATA_PLL_CFG1_0, 0x494 */
167 uint crc_pcie_pll_cfg0; /* _PCIE_PLL_CFG0_0, 0x498 */
169 uint crc_prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK_0, 0x49C */
170 uint crc_audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0_0, 0x4A0 */
171 uint crc_audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1_0, 0x4A4 */
172 uint crc_audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2_0, 0x4A8 */
173 uint crc_audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */
174 uint crc_audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */
175 uint crc_audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */
177 uint crc_plld2_base; /* _PLLD2_BASE_0, 0x4B8 */
178 uint crc_plld2_misc; /* _PLLD2_MISC_0, 0x4BC */
179 uint crc_utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4C0 */
180 uint crc_pllrefe_base; /* _PLLREFE_BASE_0, 0x4C4 */
181 uint crc_pllrefe_misc; /* _PLLREFE_MISC_0, 0x4C8 */
182 uint crs_reserved_50[7]; /* _reserved_50, 0x4CC-0x4E4 */
183 uint crc_pllc2_base; /* _PLLC2_BASE_0, 0x4E8 */
184 uint crc_pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4EC */
185 uint crc_pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4F0 */
186 uint crc_pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4F4 */
187 uint crc_pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4F8 */
188 uint crc_pllc3_base; /* _PLLC3_BASE_0, 0x4FC */
189 uint crc_pllc3_misc0; /* _PLLC3_MISC_0_0, 0x500 */
190 uint crc_pllc3_misc1; /* _PLLC3_MISC_1_0, 0x504 */
191 uint crc_pllc3_misc2; /* _PLLC3_MISC_2_0, 0x508 */
192 uint crc_pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50C */
193 uint crc_pllx_misc1; /* _PLLX_MISC_1_0, 0x510 */
194 uint crc_pllx_misc2; /* _PLLX_MISC_2_0, 0x514 */
195 uint crc_pllx_misc3; /* _PLLX_MISC_3_0, 0x518 */
196 uint crc_xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51C */
197 uint crc_xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG0_1, 0x520 */
198 uint crc_plle_aux1; /* _PLLE_AUX1_0, 0x524 */
199 uint crc_pllp_reshift; /* _PLLP_RESHIFT_0, 0x528 */
200 uint crc_utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */
201 uint crc_pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */
202 uint crc_xusb_pll_cfg0; /* _XUSB_PLL_CFG0_0, 0x534 */
203 uint crc_reserved51[1]; /* _reserved_51, 0x538 */
204 uint crc_clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53C */
205 uint crc_clk_cpug_misc; /* _CLK_CPUG_MISC_0, 0x540 */
206 uint crc_clk_cpulp_misc; /* _CLK_CPULP_MISC_0, 0x544 */
207 uint crc_pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG_0, 0x548 */
208 uint crc_pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54C */
209 uint crc_pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS_0, 0x550 */
210 uint crc_reserved52[1]; /* _reserved_52, 0x554 */
211 uint crc_super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */
212 uint crc_spare_reg0; /* _SPARE_REG0_0, 0x55C */
220 uint _rsrv32_2[25]; /* _0x59C - 0x5FC */
221 uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x67C */
224 uint crc_reserved61[5]; /* _reserved_61, 0x680 - 0x690 */
229 uint crc_clk_src_y[TEGRA_CLK_SOURCES_Y]; /* SPARE1, etc, 0x694-0x6D8 */