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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,sc8280xp-qmp-ufs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (UFS, SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
13 The QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,msm8996-qmp-ufs-phy
20 - qcom,msm8998-qmp-ufs-phy
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H A Dmediatek,ufs-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/mediatek,ufs-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MediaTek Universal Flash Storage (UFS) M-PHY
11 - Stanley Chu <stanley.chu@mediatek.com>
12 - Chunfeng Yun <chunfeng.yun@mediatek.com>
15 UFS M-PHY nodes are defined to describe on-chip UFS M-PHY hardware macro.
16 Each UFS M-PHY node should have its own node.
17 To bind UFS M-PHY with UFS host controller, the controller node should
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H A Dsamsung,ufs-phy.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC series UFS PHY
10 - Alim Akhtar <alim.akhtar@samsung.com>
13 "#phy-cells":
18 - samsung,exynos7-ufs-phy
19 - samsung,exynosautov9-ufs-phy
20 - tesla,fsd-ufs-phy
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H A Dtransmit-amplitude.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/transmit-amplitude.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common PHY and network PCS transmit amplitude property
10 Binding describing the peak-to-peak transmit amplitude for common PHYs
14 - Marek Behún <kabel@kernel.org>
17 tx-p2p-microvolt:
19 Transmit amplitude voltages in microvolts, peak-to-peak. If this property
20 contains multiple values for various PHY modes, the
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/openbmc/linux/drivers/phy/samsung/
H A DMakefile1 # SPDX-License-Identifier: GPL-2.0
2 obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
3 obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
4 obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o
5 obj-$(CONFIG_PHY_SAMSUNG_UFS) += phy-exynos-ufs.o
6 phy-exynos-ufs-y += phy-samsung-ufs.o
7 phy-exynos-ufs-y += phy-exynos7-ufs.o
8 phy-exynos-ufs-y += phy-exynosautov9-ufs.o
9 phy-exynos-ufs-y += phy-fsd-ufs.o
10 obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-exynos-usb2.o
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H A Dphy-samsung-ufs.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * UFS PHY driver for Samsung SoC
18 #include <linux/phy/phy.h>
22 #include "phy-samsung-ufs.h"
24 #define for_each_phy_lane(phy, i) \ argument
25 for (i = 0; i < (phy)->lane_cnt; i++)
27 for (; (cfg)->id; (cfg)++)
31 static void samsung_ufs_phy_config(struct samsung_ufs_phy *phy, in samsung_ufs_phy_config() argument
39 writel(cfg->val, (phy)->reg_pma + cfg->off_0); in samsung_ufs_phy_config()
42 if (cfg->id == PHY_TRSV_BLK) in samsung_ufs_phy_config()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Samsung platforms
6 tristate "Exynos SoC series Display Port PHY driver"
12 Support for Display Port PHY found on Samsung Exynos SoCs.
15 tristate "S5P/Exynos SoC series MIPI CSI-2/DSI PHY driver"
21 Support for MIPI CSI-2 and MIPI DSI DPHY found on Samsung S5P
25 bool "Exynos PCIe PHY driver"
29 Enable PCIe PHY support for Exynos SoC series.
30 This driver provides PHY interface for Exynos PCIe controller.
33 tristate "Exynos SoC series UFS PHY driver"
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/openbmc/linux/drivers/ufs/host/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0+
3 # Kernel configuration file for the UFS host controller drivers.
5 # Copyright (C) 2011-2013 Samsung India Software Operations
12 tristate "PCI bus based UFS Controller support"
15 This selects the PCI UFS Host Controller Interface. Select this if
16 you have UFS Host Controller with PCI Interface.
26 Synopsys Test Chip is a PHY for prototyping purposes.
31 tristate "Platform bus based UFS Controller support"
34 This selects the UFS host controller support. Select this if
35 you have an UFS controller on Platform bus.
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H A Dufs-exynos.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * UFS Host Controller driver for Exynos specific extensions
5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
17 #include <linux/phy/phy.h>
21 #include <ufs/ufshcd.h>
22 #include "ufshcd-pltfrm.h"
23 #include <ufs/ufshci.h>
24 #include <ufs/unipro.h>
26 #include "ufs-exynos.h"
82 /* FSYS UFS Shareability */
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H A Dufs-exynos.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * UFS Host Controller driver for Exynos specific extensions
5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
102 #define UNIPRO_PCLK_PERIOD(ufs) (NSEC_PER_SEC / ufs->pclk_rate) argument
106 /* vendor specific pre-defined parameters */
167 int (*drv_init)(struct device *dev, struct exynos_ufs *ufs);
168 int (*pre_link)(struct exynos_ufs *ufs);
169 int (*post_link)(struct exynos_ufs *ufs);
170 int (*pre_pwr_change)(struct exynos_ufs *ufs,
172 int (*post_pwr_change)(struct exynos_ufs *ufs,
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H A Dufs-qcom.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
14 #include <linux/phy/phy.h>
16 #include <linux/reset-controller.h>
21 #include <ufs/ufshcd.h>
22 #include "ufshcd-pltfrm.h"
23 #include <ufs/unipro.h>
24 #include "ufs-qcom.h"
25 #include <ufs/ufshci.h>
26 #include <ufs/ufs_quirks.h>
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/openbmc/linux/Documentation/devicetree/bindings/ufs/
H A Dsamsung,exynos-ufs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/samsung,exynos-ufs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung SoC series UFS host controller
10 - Alim Akhtar <alim.akhtar@samsung.com>
13 Each Samsung UFS host controller instance should have its own node.
16 - $ref: ufs-common.yaml
21 - samsung,exynos7-ufs
22 - samsung,exynosautov9-ufs
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H A Dqcom,ufs.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Universal Flash Storage (UFS) Controller
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Andy Gross <agross@kernel.org>
13 # Select only our matches, not all jedec,ufs-2.0
20 - compatible
25 - enum:
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H A Dcdns,ufshc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/ufs/cdns,ufshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence Universal Flash Storage (UFS) Controller
10 - Jan Kotas <jank@cadence.com>
12 # Select only our matches, not all jedec,ufs-2.0
18 - cdns,ufshc
19 - cdns,ufshc-m31-16nm
21 - compatible
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H A Dti,j721e-ufs.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ufs/ti,j721e-ufs.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: TI J721e UFS Host Controller Glue Driver
10 - Vignesh Raghavendra <vigneshr@ti.com>
15 - const: ti,j721e-ufs
19 description: address of TI UFS glue registers
23 description: phandle to the M-PHY clock
25 power-domains:
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,gcc-sc8280xp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sc8280xp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
16 See also:: include/dt-bindings/clock/qcom,gcc-sc8280xp.h
20 const: qcom,gcc-sc8280xp
24 - description: XO reference clock
25 - description: Sleep clock
26 - description: UFS memory first RX symbol clock
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H A Dqcom,gcc-sm8350.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8350.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
16 See also:: include/dt-bindings/clock/qcom,gcc-sm8350.h
20 const: qcom,gcc-sm8350
24 - description: Board XO source
25 - description: Sleep clock source
26 - description: PCIE 0 Pipe clock source (Optional clock)
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H A Dqcom,sa8775p-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sa8775p-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
16 See also:: include/dt-bindings/clock/qcom,sa8775p-gcc.h
20 const: qcom,sa8775p-gcc
24 - description: XO reference clock
25 - description: Sleep clock
26 - description: UFS memory first RX symbol clock
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H A Dqcom,sm8550-gcc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,sm8550-gcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
16 See also:: include/dt-bindings/clock/qcom,sm8550-gcc.h
20 const: qcom,sm8550-gcc
24 - description: Board XO source
25 - description: Sleep clock source
26 - description: PCIE 0 Pipe clock source
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H A Dqcom,gcc-sm8450.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/qcom,gcc-sm8450.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
16 See also:: include/dt-bindings/clock/qcom,gcc-sm8450.h
20 const: qcom,gcc-sm8450
24 - description: Board XO source
25 - description: Sleep clock source
26 - description: PCIE 0 Pipe clock source (Optional clock)
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/openbmc/linux/Documentation/scsi/
H A Dufs.rst1 .. SPDX-License-Identifier: GPL-2.0
11 2. UFS Architecture Overview
13 2.2 UFS Transport Protocol (UTP) layer
14 2.3 UFS Interconnect (UIC) Layer
16 3.1 UFS controller initialization
18 3.3 UFS error handling
21 5. UFS Reference Clock Frequency configuration
27 Universal Flash Storage (UFS) is a storage specification for flash devices.
29 embedded and removable flash memory-based storage in mobile
31 is defined by JEDEC Solid State Technology Association. UFS is based
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/openbmc/linux/drivers/phy/qualcomm/
H A Dphy-qcom-qmp-ufs.c1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
16 #include <linux/phy/phy.h>
22 #include <ufs/unipro.h>
23 #include "phy-qcom-qmp.h"
24 #include "phy-qcom-qmp-pcs-ufs-v2.h"
25 #include "phy-qcom-qmp-pcs-ufs-v3.h"
26 #include "phy-qcom-qmp-pcs-ufs-v4.h"
27 #include "phy-qcom-qmp-pcs-ufs-v5.h"
28 #include "phy-qcom-qmp-pcs-ufs-v6.h"
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Qualcomm and Atheros platforms
6 tristate "Atheros AR71XX/9XXX USB PHY driver"
12 Enable this to support the USB PHY on Atheros AR71XX/9XXX SoCs.
15 tristate "Qualcomm APQ8064 SATA SerDes/PHY driver"
22 tristate "Qualcomm eDP PHY driver"
28 Enable this driver to support the Qualcomm eDP PHY found in various
32 tristate "Qualcomm IPQ4019 USB PHY driver"
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
39 tristate "Qualcomm IPQ806x SATA SerDes/PHY driver"
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H A Dphy-qcom-qmp-pcs-ufs-v5.h1 /* Only for QMP V5 PHY - UFS PCS registers */
2 /* SPDX-License-Identifier: GPL-2.0 */
10 /* Only for QMP V5 PHY - UFS PCS registers */
/openbmc/linux/drivers/phy/mediatek/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 # Phy drivers for Mediatek devices
6 tristate "MediaTek PCIe-PHY Driver"
11 Say 'Y' here to add support for MediaTek PCIe PHY driver.
12 This driver create the basic PHY instance and provides initialize
17 tristate "MediaTek T-PHY Driver"
23 Say 'Y' here to add support for MediaTek T-PHY driver,
25 SATA, and meanwhile supports two version T-PHY which have
26 different banks layout, the T-PHY with shared banks between
27 multi-ports is first version, otherwise is second version,
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