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/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dcdns,uart.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/serial/cdns,uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Cadence UART Controller
10 - Michal Simek <michal.simek@amd.com>
15 - description: UART controller for Zynq-7xxx SoC
17 - const: xlnx,xuartps
18 - const: cdns,uart-r1p8
19 - description: UART controller for Zynq Ultrascale+ MPSoC
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/openbmc/linux/arch/xtensa/boot/dts/
H A Dcsp.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
5 compatible = "cdns,xtensa-xtfpga";
6 #address-cells = <1>;
7 #size-cells = <1>;
8 interrupt-parent = <&pic>;
20 #address-cells = <1>;
21 #size-cells = <0>;
23 compatible = "cdns,xtensa-cpu";
29 compatible = "cdns,xtensa-pic";
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/openbmc/u-boot/drivers/serial/
H A Dserial_zynq.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved.
32 u32 control; /* 0x0 - Control Register [8:0] */
33 u32 mode; /* 0x4 - Mode Register [10:0] */
35 u32 baud_rate_gen; /* 0x18 - Baud Rate Generator [15:0] */
37 u32 channel_sts; /* 0x2c - Channel Status [11:0] */
38 u32 tx_rx_fifo; /* 0x30 - FIFO [15:0] or [7:0] */
39 u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */
59 * Baud rate = ------------------ in _uart_zynq_serial_setbrg()
76 calc_bauderror = baud - calc_baud; in _uart_zynq_serial_setbrg()
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/openbmc/u-boot/arch/arm/dts/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0+
4 * Describes the hardware common to all Zynq 7000-based boards.
6 * Copyright (C) 2011 - 2015 Xilinx
10 #address-cells = <1>;
11 #size-cells = <1>;
12 compatible = "xlnx,zynq-7000";
15 #address-cells = <1>;
16 #size-cells = <0>;
19 compatible = "arm,cortex-a9";
23 clock-latency = <1000>;
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/openbmc/linux/arch/arm/boot/dts/xilinx/
H A Dzynq-7000.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2011 - 2014 Xilinx
7 #address-cells = <1>;
8 #size-cells = <1>;
9 compatible = "xlnx,zynq-7000";
12 #address-cells = <1>;
13 #size-cells = <0>;
16 compatible = "arm,cortex-a9";
20 clock-latency = <1000>;
21 cpu0-supply = <&regulator_vccpint>;
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/openbmc/linux/drivers/tty/serial/
H A Dxilinx_uartps.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Cadence UART driver (found in Xilinx Zynq)
5 * Copyright (c) 2011 - 2014 Xilinx, Inc.
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
39 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
44 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
46 /* Register offsets for the UART. */
87 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
187 * struct cdns_uart - device data
188 * @port: Pointer to the UART port
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